From 3e37e75f804cbf6b5ce04a427888fb0f0859660a Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sun, 20 Jan 2019 17:46:56 +0000
Subject: [Fix #22] Fix SAT solver equivalence checking

---
 src/VeriFuzz/Verilog/AST.hs | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Verilog/AST.hs')

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 1b2cb19..b02da1b 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -104,6 +104,8 @@ module VeriFuzz.Verilog.AST
   , declPort
   , ModConn(..)
   , modConn
+  , modConnName
+  , modExpr
   )
 where
 
@@ -398,11 +400,17 @@ instance QC.Arbitrary Port where
 -- @
 -- mod a(.y(y1), .x1(x11), .x2(x22));
 -- @
-newtype ModConn = ModConn { _modConn :: Expr }
-                deriving (Eq, Show, QC.Arbitrary)
+data ModConn = ModConn { _modConn :: Expr }
+             | ModConnNamed { _modConnName :: Identifier
+                            , _modExpr     :: Expr
+                            }
+             deriving (Eq, Show)
 
 makeLenses ''ModConn
 
+instance QC.Arbitrary ModConn where
+  arbitrary = ModConn <$> QC.arbitrary
+
 data Assign = Assign { _assignReg   :: LVal
                      , _assignDelay :: Maybe Delay
                      , _assignExpr  :: Expr
-- 
cgit