From a27290529940e7a78dfe1d736447ca6f1cf72089 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 19 Jan 2019 19:53:08 +0000
Subject: Add hlint changes

---
 src/VeriFuzz/Verilog/AST.hs | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Verilog/AST.hs')

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index dd61f03..9db4999 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -514,8 +514,7 @@ modPortGen = QC.oneof
   ]
 
 instance QC.Arbitrary ModDecl where
-  arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary
-              <*> QC.listOf1 modPortGen <*> QC.arbitrary
+  arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary <*> QC.listOf1 modPortGen <*> QC.arbitrary
 
 -- | Description of the Verilog module.
 newtype Description = Description { _getDescription :: ModDecl }
-- 
cgit