From 19955b197a0a70d626c2e3c27dc91aabcb8b3e6a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 23 Apr 2019 13:33:21 +0100 Subject: Fix code generation for always blocks with or --- src/VeriFuzz/Verilog/CodeGen.hs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/VeriFuzz/Verilog/CodeGen.hs') diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index e31866c..09d6d6f 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -146,7 +146,7 @@ expr (Str t ) = "\"" <> t <> "\"" showNum :: BitVec -> Text showNum (BitVec s n) = - minus <> showT s <> "'h" <> T.pack (showHex (abs n) "") + "(" <> minus <> showT s <> "'h" <> T.pack (showHex (abs n) "") <> ")" where minus | signum n >= 0 = "" | otherwise = "-" @@ -214,8 +214,8 @@ eventRec (EExpr e) = expr e eventRec EAll = "*" eventRec (EPosEdge i) = "posedge " <> getIdentifier i eventRec (ENegEdge i) = "negedge " <> getIdentifier i -eventRec (EOr a b) = "(" <> eventRec a <> " or " <> eventRec b <> ")" -eventRec (EComb a b) = "(" <> eventRec a <> ", " <> eventRec b <> ")" +eventRec (EOr a b ) = eventRec a <> " or " <> eventRec b +eventRec (EComb a b ) = eventRec a <> ", " <> eventRec b -- | Generates verilog code for a 'Delay'. delay :: Delay -> Text -- cgit