From 9637980a562d79582689daa5dff43814a531f900 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Sat, 11 May 2019 22:14:42 +0100
Subject: Implement module item reduction properly

---
 src/VeriFuzz/Verilog/CodeGen.hs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog/CodeGen.hs')

diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index efacd3c..71ba162 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -11,7 +11,8 @@ This module generates the code from the Verilog AST defined in
 "VeriFuzz.Verilog.AST".
 -}
 
-{-# LANGUAGE FlexibleInstances #-}
+{-# LANGUAGE DeriveDataTypeable #-}
+{-# LANGUAGE FlexibleInstances  #-}
 
 module VeriFuzz.Verilog.CodeGen
     ( -- * Code Generation
@@ -21,6 +22,7 @@ module VeriFuzz.Verilog.CodeGen
     )
 where
 
+import           Data.Data                 (Data)
 import           Data.List.NonEmpty        (NonEmpty (..), toList)
 import           Data.Text                 (Text)
 import qualified Data.Text                 as T
@@ -318,6 +320,7 @@ instance Source SourceInfo where
     genSource (SourceInfo _ src) = genSource src
 
 newtype GenVerilog a = GenVerilog { unGenVerilog :: a }
+                     deriving (Eq, Ord, Data)
 
 instance (Source a) => Show (GenVerilog a) where
     show = T.unpack . genSource . unGenVerilog
-- 
cgit