From a27290529940e7a78dfe1d736447ca6f1cf72089 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 19 Jan 2019 19:53:08 +0000 Subject: Add hlint changes --- src/VeriFuzz/Verilog/CodeGen.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/VeriFuzz/Verilog/CodeGen.hs') diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 34194a6..1551c1d 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -91,7 +91,7 @@ genModuleItem (ModInst (Identifier i) (Identifier name) conn) = i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n" genModuleItem (Initial stat ) = "initial " <> genStmnt stat genModuleItem (Always stat ) = "always " <> genStmnt stat -genModuleItem (Decl dir port) = (maybe "" makePort dir) <> genPort port <> ";\n" +genModuleItem (Decl dir port) = maybe "" makePort dir <> genPort port <> ";\n" where makePort = (<> " ") . genPortDir -- | Generate continuous assignment -- cgit