From d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 20 Jan 2019 16:49:17 +0000 Subject: Prettify files --- src/VeriFuzz/Verilog/CodeGen.hs | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/VeriFuzz/Verilog/CodeGen.hs') diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 58b1d16..0b7f422 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -155,6 +155,8 @@ genEvent :: Event -> Text genEvent (EId i ) = "@(" <> i ^. getIdentifier <> ")" genEvent (EExpr expr) = "@(" <> genExpr expr <> ")" genEvent EAll = "@*" +genEvent (EPosEdge i) = "@(posedge " <> i ^. getIdentifier <> ")" +genEvent (ENegEdge i) = "@(negedge " <> i ^. getIdentifier <> ")" -- | Generates verilog code for a 'Delay'. genDelay :: Delay -> Text -- cgit