From 43ae318ed36dcf4098a8740029bf6b4bf92e4960 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 17 Apr 2019 19:20:23 +0100
Subject: Reduce the wire size as Quartus was crashing

---
 src/VeriFuzz/Verilog/Gen.hs | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog/Gen.hs')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 46cdc25..8ff63ef 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -16,6 +16,8 @@ module VeriFuzz.Verilog.Gen
     ( -- * Generation methods
       procedural
     , proceduralIO
+    , proceduralSrc
+    , proceduralSrcIO
     , randomMod
     )
 where
@@ -104,7 +106,7 @@ largeNum :: Gen Int
 largeNum = Hog.int Hog.linearBounded
 
 wireSize :: Gen Int
-wireSize = Hog.int $ Hog.linear 2 200
+wireSize = Hog.int $ Hog.linear 2 100
 
 range :: Gen Range
 range = Range <$> fmap fromIntegral wireSize <*> pure 0
@@ -450,3 +452,9 @@ procedural top config = do
 
 proceduralIO :: T.Text -> Config -> IO Verilog
 proceduralIO t = Hog.sample . procedural t
+
+proceduralSrc :: T.Text -> Config -> Gen SourceInfo
+proceduralSrc t c = SourceInfo t <$> procedural t c
+
+proceduralSrcIO :: T.Text -> Config -> IO SourceInfo
+proceduralSrcIO t c = SourceInfo t <$> proceduralIO t c
-- 
cgit