From 705bdb142b1088676ddc3178d8677bd40ab2b1d6 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 15 Apr 2019 19:50:49 +0100 Subject: Format with brittany and add right modules --- src/VeriFuzz/Verilog/Gen.hs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'src/VeriFuzz/Verilog/Gen.hs') diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 78e278e..a6ebbd9 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -20,17 +20,17 @@ module VeriFuzz.Verilog.Gen ) where -import Control.Lens hiding (Context) -import Control.Monad (replicateM) -import Control.Monad.Trans.Class (lift) -import Control.Monad.Trans.Reader hiding (local) -import Control.Monad.Trans.State.Lazy -import Data.Foldable (fold) -import Data.List.NonEmpty (toList) -import qualified Data.Text as T -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Range as Hog +import Control.Lens hiding (Context) +import Control.Monad (replicateM) +import Control.Monad.Trans.Class (lift) +import Control.Monad.Trans.Reader hiding (local) +import Control.Monad.Trans.State.Strict +import Data.Foldable (fold) +import Data.List.NonEmpty (toList) +import qualified Data.Text as T +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import qualified Hedgehog.Range as Hog import VeriFuzz.Config import VeriFuzz.Internal import VeriFuzz.Verilog.AST -- cgit