From 7653f8fd33162b8b166a12e125c988663ec2fe79 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Mon, 8 Apr 2019 21:24:39 +0100
Subject: Create Arbitrary module

---
 src/VeriFuzz/Verilog/Gen.hs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/VeriFuzz/Verilog/Gen.hs')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 87a0a31..3afdd1a 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -30,6 +30,7 @@ import           Hedgehog                       (Gen)
 import qualified Hedgehog.Gen                   as Hog
 import           VeriFuzz.Config
 import           VeriFuzz.Internal
+import           VeriFuzz.Verilog.Arbitrary
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.Internal
 import           VeriFuzz.Verilog.Mutate
-- 
cgit