From 931b1a60643f50768eb33903e87a7471898835db Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 23 Apr 2019 10:11:27 +0100
Subject: Add event list generation for always blocks

---
 src/VeriFuzz/Verilog/Gen.hs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog/Gen.hs')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 6159766..bf9f84d 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -347,8 +347,9 @@ eventList = do
 
 always :: StateGen ModItem
 always = do
+    events <- eventList
     stat <- SeqBlock <$> some statement
-    return $ Always (EventCtrl (EPosEdge "clk") (Just stat))
+    return $ Always (EventCtrl events (Just stat))
 
 instantiate :: ModDecl -> StateGen ModItem
 instantiate (ModDecl i outP inP _ _) = do
-- 
cgit