From b281cee59daa51ba4607229092274dfa2f801806 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Sat, 13 Apr 2019 12:21:05 +0100
Subject: Fix tests passing

---
 src/VeriFuzz/Verilog/Gen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog/Gen.hs')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 8da4d1a..c325f66 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -54,7 +54,7 @@ toId = Identifier . ("w" <>) . T.pack . show
 
 toPort :: Identifier -> Gen Port
 toPort ident = do
-    i <- Hog.int $ Hog.linear 0 100
+    i <- Hog.int $ Hog.linear 1 100
     return $ wire i ident
 
 sumSize :: [Port] -> Int
-- 
cgit