From 75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 19 Jan 2019 19:35:30 +0000
Subject: Set column to 100

---
 src/VeriFuzz/Verilog/Helpers.hs | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'src/VeriFuzz/Verilog/Helpers.hs')

diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs
index 53d219b..f910924 100644
--- a/src/VeriFuzz/Verilog/Helpers.hs
+++ b/src/VeriFuzz/Verilog/Helpers.hs
@@ -45,9 +45,7 @@ testBench = ModDecl
   [ regDecl "a"
   , regDecl "b"
   , wireDecl "c"
-  , ModInst "and"
-            "and_gate"
-            [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"]
+  , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"]
   , Initial $ SeqBlock
     [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
     , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1
-- 
cgit