From dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Thu, 10 Jan 2019 15:49:13 +0000
Subject: Rename files out of the module

---
 src/VeriFuzz/Verilog/Helpers.hs | 75 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 src/VeriFuzz/Verilog/Helpers.hs

(limited to 'src/VeriFuzz/Verilog/Helpers.hs')

diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs
new file mode 100644
index 0000000..0204379
--- /dev/null
+++ b/src/VeriFuzz/Verilog/Helpers.hs
@@ -0,0 +1,75 @@
+{-|
+Module      : VeriFuzz.Verilog.Helpers
+Description : Defaults and common functions.
+Copyright   : (c) 2018-2019, Yann Herklotz Grave
+License     : BSD-3
+Maintainer  : ymherklotz [at] gmail [dot] com
+Stability   : experimental
+Portability : POSIX
+
+Defaults and common functions.
+-}
+
+module VeriFuzz.Verilog.Helpers where
+
+import           Control.Lens
+import           Data.Text            (Text)
+import qualified Data.Text
+import           VeriFuzz.Verilog.AST
+
+regDecl :: Identifier -> ModItem
+regDecl = Decl Nothing . Port (Reg False) 1
+
+wireDecl :: Identifier -> ModItem
+wireDecl = Decl Nothing . Port Wire 1
+
+modConn :: Identifier -> ModConn
+modConn = ModConn . Id
+
+-- | Create an empty module.
+emptyMod :: ModDecl
+emptyMod = ModDecl "" [] [] []
+
+-- | Set a module name for a module declaration.
+setModName :: Text -> ModDecl -> ModDecl
+setModName str = moduleId .~ Identifier str
+
+-- | Add a input port to the module declaration.
+addModPort :: Port -> ModDecl -> ModDecl
+addModPort port = modInPorts %~ (:) port
+
+addDescription :: Description -> VerilogSrc -> VerilogSrc
+addDescription desc = getVerilogSrc %~ (:) desc
+
+testBench :: ModDecl
+testBench =
+  ModDecl "main" [] []
+  [ regDecl "a"
+  , regDecl "b"
+  , wireDecl "c"
+  , ModInst "and" "and_gate"
+    [ modConn "c"
+    , modConn "a"
+    , modConn "b"
+    ]
+  , Initial $ SeqBlock
+    [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
+    , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1
+    -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display"
+    --   [ Str "%d & %d = %d"
+    --   , PrimExpr $ PrimId "a"
+    --   , PrimExpr $ PrimId "b"
+    --   , PrimExpr $ PrimId "c"
+    --   ]
+    -- , SysTaskEnable $ Task "finish" []
+    ]
+  ]
+
+addTestBench :: VerilogSrc -> VerilogSrc
+addTestBench = addDescription $ Description testBench
+
+defaultPort :: Identifier -> Port
+defaultPort = Port Wire 1
+
+portToExpr :: Port -> Expr
+portToExpr (Port _ _ id) = Id id
-- 
cgit