From fa4d1bf03003944e8a73ac4e341633020edca6af Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Thu, 10 Jan 2019 17:20:42 +0000
Subject: Fix warnings

---
 src/VeriFuzz/Verilog/Helpers.hs | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

(limited to 'src/VeriFuzz/Verilog/Helpers.hs')

diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs
index 0204379..90a5de4 100644
--- a/src/VeriFuzz/Verilog/Helpers.hs
+++ b/src/VeriFuzz/Verilog/Helpers.hs
@@ -23,9 +23,6 @@ regDecl = Decl Nothing . Port (Reg False) 1
 wireDecl :: Identifier -> ModItem
 wireDecl = Decl Nothing . Port Wire 1
 
-modConn :: Identifier -> ModConn
-modConn = ModConn . Id
-
 -- | Create an empty module.
 emptyMod :: ModDecl
 emptyMod = ModDecl "" [] [] []
@@ -48,9 +45,9 @@ testBench =
   , regDecl "b"
   , wireDecl "c"
   , ModInst "and" "and_gate"
-    [ modConn "c"
-    , modConn "a"
-    , modConn "b"
+    [ ModConn $ Id "c"
+    , ModConn $ Id "a"
+    , ModConn $ Id "b"
     ]
   , Initial $ SeqBlock
     [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
-- 
cgit