From 29804187ac1aeb6d53985e11e9591dc52633bac0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 3 Apr 2019 17:38:11 +0100
Subject: Export Vivado types and fix test failure

---
 src/VeriFuzz/Verilog/Mutate.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog/Mutate.hs')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index c72463f..69b6d57 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -105,7 +105,7 @@ allVars m =
         <> (m ^.. modInPorts . traverse . portName)
 
 -- $setup
--- >>> import VeriFuzz.CodeGen
+-- >>> import VeriFuzz.Verilog.CodeGen
 -- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [])
 -- >>> let main = (ModDecl "main" [] [] [])
 
-- 
cgit