From 4b5401ef3400413be0559dfa17718611822fc4c6 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Sat, 6 Apr 2019 21:57:48 +0100
Subject: Generate flip-flops instead of latches

---
 src/VeriFuzz/Verilog/Mutate.hs | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Verilog/Mutate.hs')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index eca472f..03ee1d0 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -206,13 +206,12 @@ makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt
 -- | Make a top module with an assert that requires @y_1@ to always be equal to
 -- @y_2@, which can then be proven using a formal verification tool.
 makeTopAssert :: ModDecl -> ModDecl
-makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop
+makeTopAssert = (modItems %~ (++ [assert])) . makeTop
     2
   where
     assert = Always . EventCtrl e . Just $ SeqBlock
         [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]]
     e      = EPosEdge "clk"
-    addClk = (defaultPort "clk" :)
 
 -- | Provide declarations for all the ports that are passed to it.
 declareMod :: [Port] -> ModDecl -> ModDecl
-- 
cgit