From 547dfe800c418165a0eb3f4667e9ea87831b375a Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 17 Apr 2019 11:02:16 +0100
Subject: Fix tests and remove Parser tests for now

---
 src/VeriFuzz/Verilog/Mutate.hs | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/VeriFuzz/Verilog/Mutate.hs')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 5fd007d..39a136e 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -108,7 +108,7 @@ allVars m =
 
 -- $setup
 -- >>> import VeriFuzz.Verilog.CodeGen
--- >>> let m = (ModDecl (Identifier "m") [Port Wire False 0 5 (Identifier "y")] [Port Wire False 0 5 "x"] [] [])
+-- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [] [])
 -- >>> let main = (ModDecl "main" [] [] [] [])
 
 -- | Add a Module Instantiation using 'ModInst' from the first module passed to
@@ -117,8 +117,8 @@ allVars m =
 --
 -- >>> render $ instantiateMod m main
 -- module main;
--- wire [4:0] y;
--- reg [4:0] x;
+-- wire [(3'h4):(1'h0)] y;
+-- reg [(3'h4):(1'h0)] x;
 -- m m1(y, x);
 -- endmodule
 -- <BLANKLINE>
@@ -179,8 +179,8 @@ filterChar t ids =
 --
 -- >>> GenVerilog $ initMod m
 -- module m(y, x);
--- output wire [4:0] y;
--- input wire [4:0] x;
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 initMod :: ModDecl -> ModDecl
-- 
cgit