From 720fa7a822a077458cf0b29e9dcdc754a881e8bd Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 5 Jun 2019 13:52:20 +0100
Subject: Format all files

---
 src/VeriFuzz/Verilog/Mutate.hs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog/Mutate.hs')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 7496935..0fb4c49 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -377,7 +377,14 @@ removeId i = transform trans
 
 combineAssigns :: Port -> [ModItem] -> [ModItem]
 combineAssigns p a =
-    a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns]
+    a
+        <> [ ModCA
+             .   ContAssign (p ^. portName)
+             .   UnOp UnXor
+             .   fold
+             $   Id
+             <$> assigns
+           ]
     where assigns = a ^.. traverse . modContAssign . contAssignNetLVal
 
 combineAssigns_ :: Bool -> Port -> [Port] -> ModItem
-- 
cgit