From 9637980a562d79582689daa5dff43814a531f900 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Sat, 11 May 2019 22:14:42 +0100
Subject: Implement module item reduction properly

---
 src/VeriFuzz/Verilog/Mutate.hs | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/VeriFuzz/Verilog/Mutate.hs')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 3f0ae83..66f3c37 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -49,6 +49,7 @@ import           VeriFuzz.Circuit.Internal
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.BitVec
+import           VeriFuzz.Verilog.CodeGen
 import           VeriFuzz.Verilog.Internal
 
 class Mutate a where
@@ -146,6 +147,9 @@ instance Mutate a => Mutate [a] where
 instance Mutate a => Mutate (Maybe a) where
     mutExpr f a = mutExpr f <$> a
 
+instance Mutate a => Mutate (GenVerilog a) where
+    mutExpr f (GenVerilog a) = GenVerilog $ mutExpr f a
+
 -- | Return if the 'Identifier' is in a 'ModDecl'.
 inPort :: Identifier -> ModDecl -> Bool
 inPort i m = inInput
-- 
cgit