From c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 5 Jun 2019 12:06:49 +0100 Subject: Add combination option --- src/VeriFuzz/Verilog/Mutate.hs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/VeriFuzz/Verilog/Mutate.hs') diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 8af0182..7496935 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -380,11 +380,11 @@ combineAssigns p a = a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal -combineAssigns_ :: Port -> [Port] -> ModItem -combineAssigns_ p ps = +combineAssigns_ :: Bool -> Port -> [Port] -> ModItem +combineAssigns_ comb p ps = ModCA . ContAssign (p ^. portName) - . UnOp UnXor + . (if comb then UnOp UnXor else id) . fold $ Id <$> ps -- cgit