From 1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 1 Feb 2019 19:39:52 +0000 Subject: More restructuring --- src/VeriFuzz/Verilog/AST.hs | 564 ---------------------------------------- src/VeriFuzz/Verilog/CodeGen.hs | 276 -------------------- src/VeriFuzz/Verilog/Helpers.hs | 72 ----- src/VeriFuzz/Verilog/Mutate.hs | 169 ------------ 4 files changed, 1081 deletions(-) delete mode 100644 src/VeriFuzz/Verilog/AST.hs delete mode 100644 src/VeriFuzz/Verilog/CodeGen.hs delete mode 100644 src/VeriFuzz/Verilog/Helpers.hs delete mode 100644 src/VeriFuzz/Verilog/Mutate.hs (limited to 'src/VeriFuzz/Verilog') diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs deleted file mode 100644 index 0f24c49..0000000 --- a/src/VeriFuzz/Verilog/AST.hs +++ /dev/null @@ -1,564 +0,0 @@ -{-| -Module : VeriFuzz.Verilog.AST -Description : Definition of the Verilog AST types. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Poratbility : POSIX - -Defines the types to build a Verilog AST. --} - -{-# LANGUAGE GeneralizedNewtypeDeriving #-} -{-# LANGUAGE TemplateHaskell #-} - -module VeriFuzz.Verilog.AST - ( -- * Top level types - VerilogSrc(..) - , getVerilogSrc - , Description(..) - , getDescription - -- * Primitives - -- ** Identifier - , Identifier(..) - , getIdentifier - -- ** Control - , Delay(..) - , getDelay - , Event(..) - -- ** Operators - , BinaryOperator(..) - , UnaryOperator(..) - -- ** Task - , Task(..) - , taskName - , taskExpr - -- ** Left hand side value - , LVal(..) - , regId - , regExprId - , regExpr - , regSizeId - , regSizeMSB - , regSizeLSB - , regConc - -- ** Ports - , PortDir(..) - , PortType(..) - , regSigned - , Port(..) - , portType - , portSize - , portName - -- * Expression - , Expr(..) - , exprSize - , exprVal - , exprId - , exprConcat - , exprUnOp - , exprPrim - , exprLhs - , exprBinOp - , exprRhs - , exprCond - , exprTrue - , exprFalse - , exprFunc - , exprBody - , exprStr - , exprWithContext - , traverseExpr - , ConstExpr(..) - , constNum - , Function (..) - -- * Assignment - , Assign(..) - , assignReg - , assignDelay - , assignExpr - , ContAssign(..) - , contAssignNetLVal - , contAssignExpr - -- * Statment - , Stmnt(..) - , statDelay - , statDStat - , statEvent - , statEStat - , statements - , stmntBA - , stmntNBA - , stmntCA - , stmntTask - , stmntSysTask - -- * Module - , ModDecl(..) - , modId - , modOutPorts - , modInPorts - , modItems - , ModItem(..) - , _ModCA - , modInstId - , modInstName - , modInstConns - , declDir - , declPort - , ModConn(..) - , modConn - , modConnName - , modExpr - ) -where - -import Control.Lens (makeLenses, makePrisms) -import Control.Monad (replicateM) -import Data.String (IsString, fromString) -import Data.Text (Text) -import qualified Data.Text as T -import Data.Traversable (sequenceA) -import qualified Test.QuickCheck as QC - -positiveArb :: (QC.Arbitrary a, Ord a, Num a) => QC.Gen a -positiveArb = QC.suchThat QC.arbitrary (> 0) - --- | Identifier in Verilog. This is just a string of characters that can either --- be lowercase and uppercase for now. This might change in the future though, --- as Verilog supports many more characters in Identifiers. -newtype Identifier = Identifier { _getIdentifier :: Text } - deriving (Eq, Show, IsString, Semigroup, Monoid) - -makeLenses ''Identifier - -instance QC.Arbitrary Identifier where - arbitrary = do - l <- QC.choose (2, 10) - Identifier . T.pack <$> replicateM l (QC.elements ['a'..'z']) - --- | Verilog syntax for adding a delay, which is represented as @#num@. -newtype Delay = Delay { _getDelay :: Int } - deriving (Eq, Show, Num) - -makeLenses ''Delay - -instance QC.Arbitrary Delay where - arbitrary = Delay <$> positiveArb - --- | Verilog syntax for an event, such as @\@x@, which is used for always blocks -data Event = EId Identifier - | EExpr Expr - | EAll - | EPosEdge Identifier - | ENegEdge Identifier - deriving (Eq, Show) - -instance QC.Arbitrary Event where - arbitrary = EId <$> QC.arbitrary - --- | Binary operators that are currently supported in the verilog generation. -data BinaryOperator = BinPlus -- ^ @+@ - | BinMinus -- ^ @-@ - | BinTimes -- ^ @*@ - | BinDiv -- ^ @/@ - | BinMod -- ^ @%@ - | BinEq -- ^ @==@ - | BinNEq -- ^ @!=@ - | BinCEq -- ^ @===@ - | BinCNEq -- ^ @!==@ - | BinLAnd -- ^ @&&@ - | BinLOr -- ^ @||@ - | BinLT -- ^ @<@ - | BinLEq -- ^ @<=@ - | BinGT -- ^ @>@ - | BinGEq -- ^ @>=@ - | BinAnd -- ^ @&@ - | BinOr -- ^ @|@ - | BinXor -- ^ @^@ - | BinXNor -- ^ @^~@ - | BinXNorInv -- ^ @~^@ - | BinPower -- ^ @**@ - | BinLSL -- ^ @<<@ - | BinLSR -- ^ @>>@ - | BinASL -- ^ @<<<@ - | BinASR -- ^ @>>>@ - deriving (Eq, Show) - -instance QC.Arbitrary BinaryOperator where - arbitrary = QC.elements - [ BinPlus - , BinMinus - , BinTimes - , BinDiv - , BinMod - , BinEq - , BinNEq - , BinCEq - , BinCNEq - , BinLAnd - , BinLOr - , BinLT - , BinLEq - , BinGT - , BinGEq - , BinAnd - , BinOr - , BinXor - , BinXNor - , BinXNorInv - , BinPower - , BinLSL - , BinLSR - , BinASL - , BinASR - ] - --- | Unary operators that are currently supported by the generator. -data UnaryOperator = UnPlus -- ^ @+@ - | UnMinus -- ^ @-@ - | UnNot -- ^ @!@ - | UnAnd -- ^ @&@ - | UnNand -- ^ @~&@ - | UnOr -- ^ @|@ - | UnNor -- ^ @~|@ - | UnXor -- ^ @^@ - | UnNxor -- ^ @~^@ - | UnNxorInv -- ^ @^~@ - deriving (Eq, Show) - -instance QC.Arbitrary UnaryOperator where - arbitrary = QC.elements - [ UnPlus - , UnMinus - , UnNot - , UnAnd - , UnNand - , UnOr - , UnNor - , UnXor - , UnNxor - , UnNxorInv - ] - -data Function = SignedFunc - | UnSignedFunc - deriving (Eq, Show) - -instance QC.Arbitrary Function where - arbitrary = QC.elements - [ SignedFunc - , UnSignedFunc - ] - --- | Verilog expression, which can either be a primary expression, unary --- expression, binary operator expression or a conditional expression. -data Expr = Number { _exprSize :: Int - , _exprVal :: Integer - } - | Id { _exprId :: Identifier } - | Concat { _exprConcat :: [Expr] } - | UnOp { _exprUnOp :: UnaryOperator - , _exprPrim :: Expr - } - | BinOp { _exprLhs :: Expr - , _exprBinOp :: BinaryOperator - , _exprRhs :: Expr - } - | Cond { _exprCond :: Expr - , _exprTrue :: Expr - , _exprFalse :: Expr - } - | Func { _exprFunc :: Function - , _exprBody :: Expr - } - | Str { _exprStr :: Text } - deriving (Eq, Show) - -instance Num Expr where - a + b = BinOp a BinPlus b - a - b = BinOp a BinMinus b - a * b = BinOp a BinTimes b - negate = UnOp UnMinus - abs = undefined - signum = undefined - fromInteger = Number 32 . fromInteger - -instance Semigroup Expr where - (Concat a) <> (Concat b) = Concat $ a <> b - (Concat a) <> b = Concat $ a <> [b] - a <> (Concat b) = Concat $ a : b - a <> b = Concat [a, b] - -instance Monoid Expr where - mempty = Concat [] - -instance IsString Expr where - fromString = Str . fromString - -exprSafeList :: [QC.Gen Expr] -exprSafeList = - [ Number <$> positiveArb <*> QC.arbitrary - -- , Str <$> QC.arbitrary - ] - -exprRecList :: (Int -> QC.Gen Expr) -> [QC.Gen Expr] -exprRecList subexpr = - [ Number <$> positiveArb <*> QC.arbitrary - , Concat <$> QC.listOf1 (subexpr 8) - , UnOp - <$> QC.arbitrary - <*> subexpr 2 - -- , Str <$> QC.arbitrary - , BinOp <$> subexpr 2 <*> QC.arbitrary <*> subexpr 2 - , Cond <$> subexpr 3 <*> subexpr 3 <*> subexpr 3 - , Func <$> QC.arbitrary <*> subexpr 2 - ] - -expr :: Int -> QC.Gen Expr -expr n - | n == 0 = QC.oneof $ (Id <$> QC.arbitrary) : exprSafeList - | n > 0 = QC.oneof $ (Id <$> QC.arbitrary) : exprRecList subexpr - | otherwise = expr 0 - where subexpr y = expr (n `div` y) - -exprWithContext :: [Identifier] -> Int -> QC.Gen Expr -exprWithContext l n - | n == 0 = QC.oneof $ (Id <$> QC.elements l) : exprSafeList - | n > 0 = QC.oneof $ (Id <$> QC.elements l) : exprRecList subexpr - | otherwise = exprWithContext l 0 - where subexpr y = exprWithContext l (n `div` y) - -instance QC.Arbitrary Expr where - arbitrary = QC.sized expr - -traverseExpr :: (Applicative f) => (Expr -> f Expr) -> Expr -> f Expr -traverseExpr f (Concat e ) = Concat <$> sequenceA (f <$> e) -traverseExpr f (UnOp un e ) = UnOp un <$> f e -traverseExpr f (BinOp l op r) = BinOp <$> f l <*> pure op <*> f r -traverseExpr f (Cond c l r) = Cond <$> f c <*> f l <*> f r -traverseExpr f (Func fn e ) = Func fn <$> f e -traverseExpr _ e = pure e - -makeLenses ''Expr - --- | Constant expression, which are known before simulation at compilation time. -newtype ConstExpr = ConstExpr { _constNum :: Int } - deriving (Eq, Show, Num, QC.Arbitrary) - -makeLenses ''ConstExpr - -data Task = Task { _taskName :: Identifier - , _taskExpr :: [Expr] - } deriving (Eq, Show) - -makeLenses ''Task - -instance QC.Arbitrary Task where - arbitrary = Task <$> QC.arbitrary <*> QC.arbitrary - --- | Type that represents the left hand side of an assignment, which can be a --- concatenation such as in: --- --- @ --- {a, b, c} = 32'h94238; --- @ -data LVal = RegId { _regId :: Identifier} - | RegExpr { _regExprId :: Identifier - , _regExpr :: Expr - } - | RegSize { _regSizeId :: Identifier - , _regSizeMSB :: ConstExpr - , _regSizeLSB :: ConstExpr - } - | RegConcat { _regConc :: [Expr] } - deriving (Eq, Show) - -makeLenses ''LVal - -instance QC.Arbitrary LVal where - arbitrary = QC.oneof [ RegId <$> QC.arbitrary - , RegExpr <$> QC.arbitrary <*> QC.arbitrary - , RegSize <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary - ] - -instance IsString LVal where - fromString = RegId . fromString - --- | Different port direction that are supported in Verilog. -data PortDir = PortIn -- ^ Input direction for port (@input@). - | PortOut -- ^ Output direction for port (@output@). - | PortInOut -- ^ Inout direction for port (@inout@). - deriving (Eq, Show) - -instance QC.Arbitrary PortDir where - arbitrary = QC.elements [PortIn, PortOut, PortInOut] - --- | Currently, only @wire@ and @reg@ are supported, as the other net types are --- not that common and not a priority. -data PortType = Wire - | Reg { _regSigned :: Bool } - deriving (Eq, Show) - -instance QC.Arbitrary PortType where - arbitrary = QC.oneof [pure Wire, Reg <$> QC.arbitrary] - -makeLenses ''PortType - --- | Port declaration. It contains information about the type of the port, the --- size, and the port name. It used to also contain information about if it was --- an input or output port. However, this is not always necessary and was more --- cumbersome than useful, as a lot of ports can be declared without input and --- output port. --- --- This is now implemented inside 'ModDecl' itself, which uses a list of output --- and input ports. -data Port = Port { _portType :: PortType - , _portSize :: Int - , _portName :: Identifier - } deriving (Eq, Show) - -makeLenses ''Port - -instance QC.Arbitrary Port where - arbitrary = Port <$> QC.arbitrary <*> positiveArb <*> QC.arbitrary - --- | This is currently a type because direct module declaration should also be --- added: --- --- @ --- mod a(.y(y1), .x1(x11), .x2(x22)); --- @ -data ModConn = ModConn { _modConn :: Expr } - | ModConnNamed { _modConnName :: Identifier - , _modExpr :: Expr - } - deriving (Eq, Show) - -makeLenses ''ModConn - -instance QC.Arbitrary ModConn where - arbitrary = ModConn <$> QC.arbitrary - -data Assign = Assign { _assignReg :: LVal - , _assignDelay :: Maybe Delay - , _assignExpr :: Expr - } deriving (Eq, Show) - -makeLenses ''Assign - -instance QC.Arbitrary Assign where - arbitrary = Assign <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary - -data ContAssign = ContAssign { _contAssignNetLVal :: Identifier - , _contAssignExpr :: Expr - } deriving (Eq, Show) - -makeLenses ''ContAssign - -instance QC.Arbitrary ContAssign where - arbitrary = ContAssign <$> QC.arbitrary <*> QC.arbitrary - --- | Statements in Verilog. -data Stmnt = TimeCtrl { _statDelay :: Delay - , _statDStat :: Maybe Stmnt - } -- ^ Time control (@#NUM@) - | EventCtrl { _statEvent :: Event - , _statEStat :: Maybe Stmnt - } - | SeqBlock { _statements :: [Stmnt] } -- ^ Sequential block (@begin ... end@) - | BlockAssign { _stmntBA :: Assign } -- ^ blocking assignment (@=@) - | NonBlockAssign { _stmntNBA :: Assign } -- ^ Non blocking assignment (@<=@) - | StatCA { _stmntCA :: ContAssign } -- ^ Stmnt continuous assignment. May not be correct. - | TaskEnable { _stmntTask :: Task} - | SysTaskEnable { _stmntSysTask :: Task} - deriving (Eq, Show) - -makeLenses ''Stmnt - -instance Semigroup Stmnt where - (SeqBlock a) <> (SeqBlock b) = SeqBlock $ a <> b - (SeqBlock a) <> b = SeqBlock $ a <> [b] - a <> (SeqBlock b) = SeqBlock $ a : b - a <> b = SeqBlock [a, b] - -instance Monoid Stmnt where - mempty = SeqBlock [] - -statement :: Int -> QC.Gen Stmnt -statement n - | n == 0 = QC.oneof - [ BlockAssign <$> QC.arbitrary - , NonBlockAssign <$> QC.arbitrary - -- , StatCA <$> QC.arbitrary - , TaskEnable <$> QC.arbitrary - , SysTaskEnable <$> QC.arbitrary - ] - | n > 0 = QC.oneof - [ TimeCtrl <$> QC.arbitrary <*> (Just <$> substat 2) - , SeqBlock <$> QC.listOf1 (substat 4) - , BlockAssign <$> QC.arbitrary - , NonBlockAssign <$> QC.arbitrary - -- , StatCA <$> QC.arbitrary - , TaskEnable <$> QC.arbitrary - , SysTaskEnable <$> QC.arbitrary - ] - | otherwise = statement 0 - where substat y = statement (n `div` y) - -instance QC.Arbitrary Stmnt where - arbitrary = QC.sized statement - --- | Module item which is the body of the module expression. -data ModItem = ModCA ContAssign - | ModInst { _modInstId :: Identifier - , _modInstName :: Identifier - , _modInstConns :: [ModConn] - } - | Initial Stmnt - | Always Stmnt - | Decl { _declDir :: Maybe PortDir - , _declPort :: Port - } - deriving (Eq, Show) - -makeLenses ''ModItem -makePrisms ''ModItem - -instance QC.Arbitrary ModItem where - arbitrary = QC.oneof [ ModCA <$> QC.arbitrary - , ModInst <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary - , Initial <$> QC.arbitrary - , Always <$> (EventCtrl <$> QC.arbitrary <*> QC.arbitrary) - , Decl <$> pure Nothing <*> QC.arbitrary - ] - --- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' -data ModDecl = ModDecl { _modId :: Identifier - , _modOutPorts :: [Port] - , _modInPorts :: [Port] - , _modItems :: [ModItem] - } deriving (Eq, Show) - -makeLenses ''ModDecl - -modPortGen :: QC.Gen Port -modPortGen = QC.oneof - [ Port Wire <$> positiveArb <*> QC.arbitrary - , Port <$> (Reg <$> QC.arbitrary) <*> positiveArb <*> QC.arbitrary - ] - -instance QC.Arbitrary ModDecl where - arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary <*> QC.listOf1 modPortGen <*> QC.arbitrary - --- | Description of the Verilog module. -newtype Description = Description { _getDescription :: ModDecl } - deriving (Eq, Show, QC.Arbitrary) - -makeLenses ''Description - --- | The complete sourcetext for the Verilog module. -newtype VerilogSrc = VerilogSrc { _getVerilogSrc :: [Description] } - deriving (Eq, Show, QC.Arbitrary, Semigroup, Monoid) - -makeLenses ''VerilogSrc diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs deleted file mode 100644 index 3253f86..0000000 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ /dev/null @@ -1,276 +0,0 @@ -{-| -Module : VeriFuzz.Verilog.CodeGen -Description : Code generation for Verilog AST. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Portability : POSIX - -This module generates the code from the Verilog AST defined in -"VeriFuzz.Verilog.AST". --} - -{-# LANGUAGE FlexibleInstances #-} - -module VeriFuzz.Verilog.CodeGen where - -import Control.Lens (view, (^.)) -import Data.Foldable (fold) -import Data.Text (Text) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Numeric (showHex) -import Test.QuickCheck (Arbitrary, arbitrary) -import VeriFuzz.Verilog.AST - --- | 'Source' class which determines that source code is able to be generated --- from the data structure using 'genSource'. This will be stored in 'Text' and --- can then be processed further. -class Source a where - genSource :: a -> Text - --- | Inserts commas between '[Text]' and except the last one. -comma :: [Text] -> Text -comma = T.intercalate ", " - --- | Show function for 'Text' -showT :: (Show a) => a -> Text -showT = T.pack . show - --- | Map a 'Maybe Stmnt' to 'Text'. If it is 'Just stmnt', the generated --- statements are returned. If it is 'Nothing', then @;\n@ is returned. -defMap :: Maybe Stmnt -> Text -defMap = maybe ";\n" genStmnt - --- | Convert the 'VerilogSrc' type to 'Text' so that it can be rendered. -genVerilogSrc :: VerilogSrc -> Text -genVerilogSrc source = fold $ genDescription <$> source ^. getVerilogSrc - --- | Generate the 'Description' to 'Text'. -genDescription :: Description -> Text -genDescription desc = genModuleDecl $ desc ^. getDescription - --- | Generate the 'ModDecl' for a module and convert it to 'Text'. -genModuleDecl :: ModDecl -> Text -genModuleDecl m = - "module " <> m ^. modId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n" - where - ports | noIn && noOut = "" - | otherwise = "(" <> comma (genModPort <$> outIn) <> ")" - modI = fold $ genModuleItem <$> m ^. modItems - noOut = null $ m ^. modOutPorts - noIn = null $ m ^. modInPorts - outIn = (m ^. modOutPorts) ++ (m ^. modInPorts) - --- | Conversts 'Port' to 'Text' for the module list, which means it only --- generates a list of identifiers. -genModPort :: Port -> Text -genModPort port = port ^. portName . getIdentifier - --- | Generate the 'Port' description. -genPort :: Port -> Text -genPort port = t <> size <> name - where - t = (<> " ") . genPortType $ port ^. portType - size | port ^. portSize > 1 = "[" <> showT (port ^. portSize - 1) <> ":0] " - | otherwise = "" - name = port ^. portName . getIdentifier - --- | Convert the 'PortDir' type to 'Text'. -genPortDir :: PortDir -> Text -genPortDir PortIn = "input" -genPortDir PortOut = "output" -genPortDir PortInOut = "inout" - --- | Generate a 'ModItem'. -genModuleItem :: ModItem -> Text -genModuleItem (ModCA ca) = genContAssign ca -genModuleItem (ModInst (Identifier i) (Identifier name) conn) = - i <> " " <> name <> "(" <> comma (genModConn <$> conn) <> ")" <> ";\n" -genModuleItem (Initial stat ) = "initial " <> genStmnt stat -genModuleItem (Always stat ) = "always " <> genStmnt stat -genModuleItem (Decl dir port) = maybe "" makePort dir <> genPort port <> ";\n" - where makePort = (<> " ") . genPortDir - -genModConn :: ModConn -> Text -genModConn (ModConn c) = - genExpr c -genModConn (ModConnNamed n c) = - "." <> n ^. getIdentifier <> "(" <> genExpr c <> ")" - --- | Generate continuous assignment -genContAssign :: ContAssign -> Text -genContAssign (ContAssign val e) = "assign " <> name <> " = " <> expr <> ";\n" - where - name = val ^. getIdentifier - expr = genExpr e - --- | Generate 'Function' to 'Text' -genFunc :: Function -> Text -genFunc SignedFunc = "$signed" -genFunc UnSignedFunc = "$unsigned" - --- | Generate 'Expr' to 'Text'. -genExpr :: Expr -> Text -genExpr (BinOp eRhs bin eLhs) = "(" <> genExpr eRhs <> genBinaryOperator bin <> genExpr eLhs <> ")" -genExpr (Number s n ) = minus <> showT s <> "'h" <> T.pack (showHex (abs n) "") - where minus | signum n > 0 = "" | otherwise = "-" -genExpr (Id i ) = i ^. getIdentifier -genExpr (Concat c ) = "{" <> comma (genExpr <$> c) <> "}" -genExpr (UnOp u e ) = "(" <> genUnaryOperator u <> genExpr e <> ")" -genExpr (Cond l t f ) = "(" <> genExpr l <> " ? " <> genExpr t <> " : " <> genExpr f <> ")" -genExpr (Func f e ) = genFunc f <> "(" <> genExpr e <> ")" -genExpr (Str t ) = "\"" <> t <> "\"" - --- | Convert 'BinaryOperator' to 'Text'. -genBinaryOperator :: BinaryOperator -> Text -genBinaryOperator BinPlus = " + " -genBinaryOperator BinMinus = " - " -genBinaryOperator BinTimes = " * " -genBinaryOperator BinDiv = " / " -genBinaryOperator BinMod = " % " -genBinaryOperator BinEq = " == " -genBinaryOperator BinNEq = " != " -genBinaryOperator BinCEq = " === " -genBinaryOperator BinCNEq = " !== " -genBinaryOperator BinLAnd = " && " -genBinaryOperator BinLOr = " || " -genBinaryOperator BinLT = " < " -genBinaryOperator BinLEq = " <= " -genBinaryOperator BinGT = " > " -genBinaryOperator BinGEq = " >= " -genBinaryOperator BinAnd = " & " -genBinaryOperator BinOr = " | " -genBinaryOperator BinXor = " ^ " -genBinaryOperator BinXNor = " ^~ " -genBinaryOperator BinXNorInv = " ~^ " -genBinaryOperator BinPower = " ** " -genBinaryOperator BinLSL = " << " -genBinaryOperator BinLSR = " >> " -genBinaryOperator BinASL = " <<< " -genBinaryOperator BinASR = " >>> " - --- | Convert 'UnaryOperator' to 'Text'. -genUnaryOperator :: UnaryOperator -> Text -genUnaryOperator UnPlus = "+" -genUnaryOperator UnMinus = "-" -genUnaryOperator UnNot = "!" -genUnaryOperator UnAnd = "&" -genUnaryOperator UnNand = "~&" -genUnaryOperator UnOr = "|" -genUnaryOperator UnNor = "~|" -genUnaryOperator UnXor = "^" -genUnaryOperator UnNxor = "~^" -genUnaryOperator UnNxorInv = "^~" - --- | Generate verilog code for an 'Event'. -genEvent :: Event -> Text -genEvent (EId i ) = "@(" <> i ^. getIdentifier <> ")" -genEvent (EExpr expr) = "@(" <> genExpr expr <> ")" -genEvent EAll = "@*" -genEvent (EPosEdge i) = "@(posedge " <> i ^. getIdentifier <> ")" -genEvent (ENegEdge i) = "@(negedge " <> i ^. getIdentifier <> ")" - --- | Generates verilog code for a 'Delay'. -genDelay :: Delay -> Text -genDelay (Delay i) = "#" <> showT i - --- | Generate the verilog code for an 'LVal'. -genLVal :: LVal -> Text -genLVal (RegId i ) = i ^. getIdentifier -genLVal (RegExpr i expr) = i ^. getIdentifier <> " [" <> genExpr expr <> "]" -genLVal (RegSize i msb lsb) = - i ^. getIdentifier <> " [" <> genConstExpr msb <> ":" <> genConstExpr lsb <> "]" -genLVal (RegConcat e) = "{" <> comma (genExpr <$> e) <> "}" - -genConstExpr :: ConstExpr -> Text -genConstExpr (ConstExpr num) = showT num - -genPortType :: PortType -> Text -genPortType Wire = "wire" -genPortType (Reg signed) | signed = "reg signed" - | otherwise = "reg" - -genAssign :: Text -> Assign -> Text -genAssign op (Assign r d e) = genLVal r <> op <> maybe "" genDelay d <> genExpr e - -genStmnt :: Stmnt -> Text -genStmnt (TimeCtrl d stat ) = genDelay d <> " " <> defMap stat -genStmnt (EventCtrl e stat ) = genEvent e <> " " <> defMap stat -genStmnt (SeqBlock s ) = "begin\n" <> fold (genStmnt <$> s) <> "end\n" -genStmnt (BlockAssign a ) = genAssign " = " a <> ";\n" -genStmnt (NonBlockAssign a ) = genAssign " <= " a <> ";\n" -genStmnt (StatCA a ) = genContAssign a -genStmnt (TaskEnable task) = genTask task <> ";\n" -genStmnt (SysTaskEnable task) = "$" <> genTask task <> ";\n" - -genTask :: Task -> Text -genTask (Task name expr) | null expr = i - | otherwise = i <> "(" <> comma (genExpr <$> expr) <> ")" - where i = name ^. getIdentifier - --- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'. -render :: (Source a) => a -> IO () -render = T.putStrLn . genSource - --- Instances - -instance Source Identifier where - genSource = view getIdentifier - -instance Source Task where - genSource = genTask - -instance Source Stmnt where - genSource = genStmnt - -instance Source PortType where - genSource = genPortType - -instance Source ConstExpr where - genSource = genConstExpr - -instance Source LVal where - genSource = genLVal - -instance Source Delay where - genSource = genDelay - -instance Source Event where - genSource = genEvent - -instance Source UnaryOperator where - genSource = genUnaryOperator - -instance Source Expr where - genSource = genExpr - -instance Source ContAssign where - genSource = genContAssign - -instance Source ModItem where - genSource = genModuleItem - -instance Source PortDir where - genSource = genPortDir - -instance Source Port where - genSource = genPort - -instance Source ModDecl where - genSource = genModuleDecl - -instance Source Description where - genSource = genDescription - -instance Source VerilogSrc where - genSource = genVerilogSrc - -newtype GenVerilog a = GenVerilog { unGenVerilog :: a } - -instance (Source a) => Show (GenVerilog a) where - show = T.unpack . genSource . unGenVerilog - -instance (Arbitrary a) => Arbitrary (GenVerilog a) where - arbitrary = GenVerilog <$> arbitrary diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs deleted file mode 100644 index 99e5f38..0000000 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ /dev/null @@ -1,72 +0,0 @@ -{-| -Module : VeriFuzz.Verilog.Helpers -Description : Defaults and common functions. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Portability : POSIX - -Defaults and common functions. --} - -module VeriFuzz.Verilog.Helpers where - -import Control.Lens -import Data.Text (Text) -import VeriFuzz.Verilog.AST - -regDecl :: Identifier -> ModItem -regDecl = Decl Nothing . Port (Reg False) 1 - -wireDecl :: Identifier -> ModItem -wireDecl = Decl Nothing . Port Wire 1 - --- | Create an empty module. -emptyMod :: ModDecl -emptyMod = ModDecl "" [] [] [] - --- | Set a module name for a module declaration. -setModName :: Text -> ModDecl -> ModDecl -setModName str = modId .~ Identifier str - --- | Add a input port to the module declaration. -addModPort :: Port -> ModDecl -> ModDecl -addModPort port = modInPorts %~ (:) port - -addDescription :: Description -> VerilogSrc -> VerilogSrc -addDescription desc = getVerilogSrc %~ (:) desc - -testBench :: ModDecl -testBench = ModDecl - "main" - [] - [] - [ regDecl "a" - , regDecl "b" - , wireDecl "c" - , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] - , Initial $ SeqBlock - [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 - , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 - -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" - -- [ Str "%d & %d = %d" - -- , PrimExpr $ PrimId "a" - -- , PrimExpr $ PrimId "b" - -- , PrimExpr $ PrimId "c" - -- ] - -- , SysTaskEnable $ Task "finish" [] - ] - ] - -addTestBench :: VerilogSrc -> VerilogSrc -addTestBench = addDescription $ Description testBench - -defaultPort :: Identifier -> Port -defaultPort = Port Wire 1 - -portToExpr :: Port -> Expr -portToExpr (Port _ _ i) = Id i - -modName :: ModDecl -> Text -modName = view $ modId . getIdentifier diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs deleted file mode 100644 index 3e03a02..0000000 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ /dev/null @@ -1,169 +0,0 @@ -{-| -Module : VeriFuzz.Verilog.Mutation -Description : Functions to mutate the Verilog AST. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Portability : POSIX - -Functions to mutate the Verilog AST from "VeriFuzz.Verilog.AST" to generate more -random patterns, such as nesting wires instead of creating new ones. --} - -module VeriFuzz.Verilog.Mutate where - -import Control.Lens -import Data.Maybe (catMaybes, fromMaybe) -import Data.Text (Text) -import qualified Data.Text as T -import VeriFuzz.Internal.Gen -import VeriFuzz.Internal.Shared -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen - --- | Return if the 'Identifier' is in a 'ModDecl'. -inPort :: Identifier -> ModDecl -> Bool -inPort i m = inInput - where inInput = any (\a -> a ^. portName == i) $ - m ^. modInPorts ++ m ^. modOutPorts - --- | Find the last assignment of a specific wire/reg to an expression, and --- returns that expression. -findAssign :: Identifier -> [ModItem] -> Maybe Expr -findAssign i items = safe last . catMaybes $ isAssign <$> items - where - isAssign (ModCA (ContAssign val expr)) - | val == i = Just expr - | otherwise = Nothing - isAssign _ = Nothing - --- | Transforms an expression by replacing an Identifier with an --- expression. This is used inside 'transformOf' and 'traverseExpr' to replace --- the 'Identifier' recursively. -idTrans :: Identifier -> Expr -> Expr -> Expr -idTrans i expr (Id id') | id' == i = expr - | otherwise = Id id' -idTrans _ _ e = e - --- | Replaces the identifier recursively in an expression. -replace :: Identifier -> Expr -> Expr -> Expr -replace = (transformOf traverseExpr .) . idTrans - --- | Nest expressions for a specific 'Identifier'. If the 'Identifier' is not --- found, the AST is not changed. --- --- This could be improved by instead of only using the last assignment to the --- wire that one finds, to use the assignment to the wire before the current --- expression. This would require a different approach though. -nestId :: Identifier -> ModDecl -> ModDecl -nestId i m - | not $ inPort i m - = let expr = fromMaybe def . findAssign i $ m ^. modItems in m & get %~ replace i expr - | otherwise - = m - where - get = modItems . traverse . _ModCA . contAssignExpr - def = Id i - --- | Replaces an identifier by a expression in all the module declaration. -nestSource :: Identifier -> VerilogSrc -> VerilogSrc -nestSource i src = src & getVerilogSrc . traverse . getDescription %~ nestId i - --- | Nest variables in the format @w[0-9]*@ up to a certain number. -nestUpTo :: Int -> VerilogSrc -> VerilogSrc -nestUpTo i src = foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i] - -allVars :: ModDecl -> [Identifier] -allVars m = (m ^.. modOutPorts . traverse . portName) ++ (m ^.. modInPorts . traverse . portName) --- $setup --- >>> let m = (ModDecl (Identifier "m") [Port Wire 5 (Identifier "y")] [Port Wire 5 "x"] []) --- >>> let main = (ModDecl "main" [] [] []) - --- | Add a Module Instantiation using 'ModInst' from the first module passed to --- it to the body of the second module. It first has to make all the inputs into --- @reg@. --- --- >>> render $ instantiateMod m main --- module main; --- wire [4:0] y; --- reg [4:0] x; --- m m1(y, x); --- endmodule --- -instantiateMod :: ModDecl -> ModDecl -> ModDecl -instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++) - where - out = Decl Nothing <$> m ^. modOutPorts - regIn = Decl Nothing <$> (m ^. modInPorts & traverse . portType .~ Reg False) - inst = ModInst (m ^. modId) (m ^. modId <> (Identifier . showT $ count + 1)) conns - count = length . filter (== m ^. modId) $ main ^.. modItems . traverse . modInstId - conns = ModConn . Id <$> allVars m - --- | Instantiate without adding wire declarations. It also does not count the --- current instantiations of the same module. --- --- >>> render $ instantiateMod_ m --- m m(y, x); --- -instantiateMod_ :: ModDecl -> ModItem -instantiateMod_ m = ModInst (m ^. modId) (m ^. modId) conns - where - conns = - ModConn - . Id - <$> (m ^.. modOutPorts . traverse . portName) - ++ (m ^.. modInPorts . traverse . portName) - --- | Instantiate without adding wire declarations. It also does not count the --- current instantiations of the same module. --- --- >>> render $ instantiateModSpec_ "_" m --- m m(.y(y), .x(x)); --- -instantiateModSpec_ :: Text -> ModDecl -> ModItem -instantiateModSpec_ outChar m = ModInst (m ^. modId) (m ^. modId) conns - where - conns = - zipWith ModConnNamed ids (Id <$> instIds) - ids = (filterChar outChar $ name modOutPorts) ++ (name modInPorts) - instIds = (name modOutPorts) ++ (name modInPorts) - name v = m ^.. v . traverse . portName - -filterChar :: Text -> [Identifier] -> [Identifier] -filterChar t ids = - ids & traverse . getIdentifier %~ (\x -> fromMaybe x . safe head $ T.splitOn t x) - --- | Initialise all the inputs and outputs to a module. --- --- >>> render $ initMod m --- module m(y, x); --- output wire [4:0] y; --- input wire [4:0] x; --- endmodule --- -initMod :: ModDecl -> ModDecl -initMod m = m & modItems %~ ((out ++ inp) ++) - where - out = Decl (Just PortOut) <$> (m ^. modOutPorts) - inp = Decl (Just PortIn) <$> (m ^. modInPorts) - -makeIdFrom :: (Show a) => a -> Identifier -> Identifier -makeIdFrom a i = (i <>) . Identifier . ("_" <>) $ showT a - --- | Make top level module for equivalence verification. Also takes in how many --- modules to instantiate. -makeTop :: Int -> ModDecl -> ModDecl -makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt - where - ys = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i] - modIt = instantiateModSpec_ "_" . modN <$> [1 .. i] - modN n = m & modId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] - -makeTopAssert :: ModDecl -> ModDecl -makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop 2 - where - assert = Always . EventCtrl e . Just $ SeqBlock - [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]] - e = EPosEdge "clk" - addClk = ((Port Wire 1 "clk") :) -- cgit