From dc15e7506096064fcb3fd297b15fc89c83ff32d0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 21 May 2019 12:00:11 +0100
Subject: Add only identity

---
 src/VeriFuzz/Verilog/Gen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 96a90f9..f4c49be 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -459,7 +459,7 @@ calcRange ps i (Range l r) = eval l - eval r + 1
 moduleDef :: Maybe Identifier -> StateGen ModDecl
 moduleDef top = do
     name     <- moduleName top
-    portList <- some $ nextPort Wire
+    portList <- Hog.list (Hog.linear 4 10) $ nextPort Wire
     mi       <- Hog.list (Hog.linear 4 100) modItem
     ps       <- many parameter
     context  <- get
-- 
cgit 


From d8dd3a04fd820fddc12d1ea46818ed1b1167e9ac Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 21 May 2019 15:24:58 +0100
Subject: Remove unused function

---
 src/VeriFuzz/Verilog/Gen.hs | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index f4c49be..bd80c3d 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -231,9 +231,6 @@ someI m f = do
     amount <- gen $ Hog.int (Hog.linear 1 m)
     replicateM amount f
 
-some :: StateGen a -> StateGen [a]
-some = someI 50
-
 many :: StateGen a -> StateGen [a]
 many f = do
     amount <- gen $ Hog.int (Hog.linear 0 50)
-- 
cgit 


From e8915d759c1f6da2a1f3e8328708f40c2d203022 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 21 May 2019 20:51:20 +0100
Subject: Add necessary exports to AST and CodeGen

---
 src/VeriFuzz/Verilog/AST.hs     | 2 +-
 src/VeriFuzz/Verilog/CodeGen.hs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 306366c..7a654fd 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -492,7 +492,7 @@ newtype Verilog = Verilog { getVerilog :: [ModDecl] }
 data SourceInfo = SourceInfo { _infoTop :: {-# UNPACK #-} !Text
                              , _infoSrc :: !Verilog
                              }
-                  deriving (Eq, Show)
+                  deriving (Eq, Ord, Data, Show)
 
 $(makeLenses ''Expr)
 $(makeLenses ''ConstExpr)
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index a0ec0cc..6ef1959 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -17,7 +17,7 @@ This module generates the code from the Verilog AST defined in
 module VeriFuzz.Verilog.CodeGen
     ( -- * Code Generation
       GenVerilog(..)
-    , genSource
+    , Source(..)
     , render
     )
 where
-- 
cgit 


From 5df5d613e3aaf5f14368903b5fec5596d848ef44 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 22 May 2019 15:14:30 +0100
Subject: Change parameters of generation

---
 src/VeriFuzz/Verilog/Gen.hs | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index bd80c3d..bc40de5 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -231,11 +231,6 @@ someI m f = do
     amount <- gen $ Hog.int (Hog.linear 1 m)
     replicateM amount f
 
-many :: StateGen a -> StateGen [a]
-many f = do
-    amount <- gen $ Hog.int (Hog.linear 0 50)
-    replicateM amount f
-
 makeIdentifier :: T.Text -> StateGen Identifier
 makeIdentifier prefix = do
     context <- get
@@ -458,7 +453,7 @@ moduleDef top = do
     name     <- moduleName top
     portList <- Hog.list (Hog.linear 4 10) $ nextPort Wire
     mi       <- Hog.list (Hog.linear 4 100) modItem
-    ps       <- many parameter
+    ps       <- Hog.list (Hog.linear 0 10) parameter
     context  <- get
     let local = filter (`notElem` portList) $ _variables context
     let
@@ -473,7 +468,7 @@ moduleDef top = do
     let comb  = combineAssigns_ yport local
     return
         . declareMod local
-        . ModDecl name [yport] (clock : portList) (mi <> [comb])
+        . ModDecl name [yport] (clock : portList) (comb : mi)
         $ ps
 
 -- | Procedural generation method for random Verilog. Uses internal 'Reader' and
-- 
cgit 


From 14158fc4ef0809adbbf0b7fdd0c0d5e0fafc2435 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 24 May 2019 15:45:35 +0100
Subject: Fix used wire check for clk

---
 src/VeriFuzz/Verilog/AST.hs | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 7a654fd..f201064 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -169,6 +169,9 @@ data Event = EId {-# UNPACK #-} !Identifier
            | EComb !Event !Event
            deriving (Eq, Show, Ord, Data)
 
+instance Plated Event where
+    plate = uniplate
+
 -- | Binary operators that are currently supported in the verilog generation.
 data BinaryOperator = BinPlus    -- ^ @+@
                     | BinMinus   -- ^ @-@
-- 
cgit 


From 58eb1aea52fb57666f2f4e620e3ac9a8dd05522c Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Sun, 2 Jun 2019 12:55:19 +0100
Subject: Add XOR to the output

---
 src/VeriFuzz/Verilog/Gen.hs    | 2 +-
 src/VeriFuzz/Verilog/Mutate.hs | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index bc40de5..828224f 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -464,7 +464,7 @@ moduleDef top = do
                 ^.. traverse
                 .   portSize
     let clock = Port Wire False 1 "clk"
-    let yport = Port Wire False size "y"
+    let yport = Port Wire False 1 "y"
     let comb  = combineAssigns_ yport local
     return
         . declareMod local
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 66f3c37..8af0182 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -377,13 +377,14 @@ removeId i = transform trans
 
 combineAssigns :: Port -> [ModItem] -> [ModItem]
 combineAssigns p a =
-    a <> [ModCA . ContAssign (p ^. portName) . fold $ Id <$> assigns]
+    a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns]
     where assigns = a ^.. traverse . modContAssign . contAssignNetLVal
 
 combineAssigns_ :: Port -> [Port] -> ModItem
 combineAssigns_ p ps =
     ModCA
         .   ContAssign (p ^. portName)
+        .   UnOp UnXor
         .   fold
         $   Id
         <$> ps
-- 
cgit 


From f4dbd5a813de78a9241573a498a9bb1cb40c65f3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Sun, 2 Jun 2019 13:25:37 +0100
Subject: Remove dead code

---
 src/VeriFuzz/Verilog/Gen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 828224f..c903e28 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -464,7 +464,7 @@ moduleDef top = do
                 ^.. traverse
                 .   portSize
     let clock = Port Wire False 1 "clk"
-    let yport = Port Wire False 1 "y"
+    let yport = if True then Port Wire False 1 "y" else Port Wire False size "y"
     let comb  = combineAssigns_ yport local
     return
         . declareMod local
-- 
cgit 


From c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 5 Jun 2019 12:06:49 +0100
Subject: Add combination option

---
 src/VeriFuzz/Verilog/Gen.hs    | 3 ++-
 src/VeriFuzz/Verilog/Mutate.hs | 6 +++---
 2 files changed, 5 insertions(+), 4 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index c903e28..cb3a8ad 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -455,6 +455,7 @@ moduleDef top = do
     mi       <- Hog.list (Hog.linear 4 100) modItem
     ps       <- Hog.list (Hog.linear 0 10) parameter
     context  <- get
+    config <- lift ask
     let local = filter (`notElem` portList) $ _variables context
     let
         size =
@@ -465,7 +466,7 @@ moduleDef top = do
                 .   portSize
     let clock = Port Wire False 1 "clk"
     let yport = if True then Port Wire False 1 "y" else Port Wire False size "y"
-    let comb  = combineAssigns_ yport local
+    let comb  = combineAssigns_ (config ^. configProperty . propCombine) yport local
     return
         . declareMod local
         . ModDecl name [yport] (clock : portList) (comb : mi)
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 8af0182..7496935 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -380,11 +380,11 @@ combineAssigns p a =
     a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns]
     where assigns = a ^.. traverse . modContAssign . contAssignNetLVal
 
-combineAssigns_ :: Port -> [Port] -> ModItem
-combineAssigns_ p ps =
+combineAssigns_ :: Bool -> Port -> [Port] -> ModItem
+combineAssigns_ comb p ps =
     ModCA
         .   ContAssign (p ^. portName)
-        .   UnOp UnXor
+        .   (if comb then UnOp UnXor else id)
         .   fold
         $   Id
         <$> ps
-- 
cgit 


From f3268d934a9a2b01633b5f7a3353d1a97c40a9df Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 5 Jun 2019 13:26:47 +0100
Subject: Fix size in output wire

---
 src/VeriFuzz/Verilog/Gen.hs | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index cb3a8ad..c8860ce 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -464,9 +464,10 @@ moduleDef top = do
                 $   local
                 ^.. traverse
                 .   portSize
+    let combine = config ^. configProperty . propCombine
     let clock = Port Wire False 1 "clk"
-    let yport = if True then Port Wire False 1 "y" else Port Wire False size "y"
-    let comb  = combineAssigns_ (config ^. configProperty . propCombine) yport local
+    let yport = if combine then Port Wire False 1 "y" else Port Wire False size "y"
+    let comb  = combineAssigns_ combine yport local
     return
         . declareMod local
         . ModDecl name [yport] (clock : portList) (comb : mi)
-- 
cgit 


From 720fa7a822a077458cf0b29e9dcdc754a881e8bd Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 5 Jun 2019 13:52:20 +0100
Subject: Format all files

---
 src/VeriFuzz/Verilog/Gen.hs    | 9 +++++----
 src/VeriFuzz/Verilog/Mutate.hs | 9 ++++++++-
 2 files changed, 13 insertions(+), 5 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index c8860ce..e52a158 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -455,7 +455,7 @@ moduleDef top = do
     mi       <- Hog.list (Hog.linear 4 100) modItem
     ps       <- Hog.list (Hog.linear 0 10) parameter
     context  <- get
-    config <- lift ask
+    config   <- lift ask
     let local = filter (`notElem` portList) $ _variables context
     let
         size =
@@ -465,9 +465,10 @@ moduleDef top = do
                 ^.. traverse
                 .   portSize
     let combine = config ^. configProperty . propCombine
-    let clock = Port Wire False 1 "clk"
-    let yport = if combine then Port Wire False 1 "y" else Port Wire False size "y"
-    let comb  = combineAssigns_ combine yport local
+    let clock   = Port Wire False 1 "clk"
+    let yport =
+            if combine then Port Wire False 1 "y" else Port Wire False size "y"
+    let comb = combineAssigns_ combine yport local
     return
         . declareMod local
         . ModDecl name [yport] (clock : portList) (comb : mi)
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 7496935..0fb4c49 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -377,7 +377,14 @@ removeId i = transform trans
 
 combineAssigns :: Port -> [ModItem] -> [ModItem]
 combineAssigns p a =
-    a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns]
+    a
+        <> [ ModCA
+             .   ContAssign (p ^. portName)
+             .   UnOp UnXor
+             .   fold
+             $   Id
+             <$> assigns
+           ]
     where assigns = a ^.. traverse . modContAssign . contAssignNetLVal
 
 combineAssigns_ :: Bool -> Port -> [Port] -> ModItem
-- 
cgit 


From d32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Sat, 29 Jun 2019 20:33:59 +0100
Subject: Format files

---
 src/VeriFuzz/Verilog/AST.hs      | 16 ++++++++------
 src/VeriFuzz/Verilog/CodeGen.hs  | 14 ++++++------
 src/VeriFuzz/Verilog/Eval.hs     |  6 +++---
 src/VeriFuzz/Verilog/Gen.hs      | 21 +++++++++---------
 src/VeriFuzz/Verilog/Internal.hs |  2 +-
 src/VeriFuzz/Verilog/Mutate.hs   | 46 +++++++++++++++++++++-------------------
 src/VeriFuzz/Verilog/Parser.hs   | 23 +++++++++++---------
 src/VeriFuzz/Verilog/Quote.hs    |  4 ++--
 8 files changed, 72 insertions(+), 60 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index f201064..43063e6 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -139,14 +139,18 @@ module VeriFuzz.Verilog.AST
     )
 where
 
-import           Control.Lens             hiding ((<|))
+import           Control.Lens            hiding ( (<|) )
 import           Data.Data
 import           Data.Data.Lens
-import           Data.Functor.Foldable.TH (makeBaseFunctor)
-import           Data.List.NonEmpty       (NonEmpty (..), (<|))
-import           Data.String              (IsString, fromString)
-import           Data.Text                (Text)
-import           Data.Traversable         (sequenceA)
+import           Data.Functor.Foldable.TH       ( makeBaseFunctor )
+import           Data.List.NonEmpty             ( NonEmpty(..)
+                                                , (<|)
+                                                )
+import           Data.String                    ( IsString
+                                                , fromString
+                                                )
+import           Data.Text                      ( Text )
+import           Data.Traversable               ( sequenceA )
 import           VeriFuzz.Verilog.BitVec
 
 -- | Identifier in Verilog. This is just a string of characters that can either
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 6ef1959..82945aa 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -22,13 +22,15 @@ module VeriFuzz.Verilog.CodeGen
     )
 where
 
-import           Data.Data                 (Data)
-import           Data.List.NonEmpty        (NonEmpty (..), toList)
-import           Data.Text                 (Text)
-import qualified Data.Text                 as T
+import           Data.Data                      ( Data )
+import           Data.List.NonEmpty             ( NonEmpty(..)
+                                                , toList
+                                                )
+import           Data.Text                      ( Text )
+import qualified Data.Text                     as T
 import           Data.Text.Prettyprint.Doc
-import           Numeric                   (showHex)
-import           VeriFuzz.Internal         hiding (comma)
+import           Numeric                        ( showHex )
+import           VeriFuzz.Internal       hiding ( comma )
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.BitVec
 
diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs
index 4a43c19..d8840e3 100644
--- a/src/VeriFuzz/Verilog/Eval.hs
+++ b/src/VeriFuzz/Verilog/Eval.hs
@@ -17,9 +17,9 @@ module VeriFuzz.Verilog.Eval
 where
 
 import           Data.Bits
-import           Data.Foldable           (fold)
-import           Data.Functor.Foldable   hiding (fold)
-import           Data.Maybe              (listToMaybe)
+import           Data.Foldable                  ( fold )
+import           Data.Functor.Foldable   hiding ( fold )
+import           Data.Maybe                     ( listToMaybe )
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.BitVec
 
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index e52a158..0a6ece5 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -22,17 +22,18 @@ module VeriFuzz.Verilog.Gen
     )
 where
 
-import           Control.Lens                     hiding (Context)
-import           Control.Monad                    (replicateM)
-import           Control.Monad.Trans.Class        (lift)
-import           Control.Monad.Trans.Reader       hiding (local)
+import           Control.Lens            hiding ( Context )
+import           Control.Monad                  ( replicateM )
+import           Control.Monad.Trans.Class      ( lift )
+import           Control.Monad.Trans.Reader
+                                         hiding ( local )
 import           Control.Monad.Trans.State.Strict
-import           Data.Foldable                    (fold)
-import           Data.Functor.Foldable            (cata)
-import qualified Data.Text                        as T
-import           Hedgehog                         (Gen)
-import qualified Hedgehog.Gen                     as Hog
-import qualified Hedgehog.Range                   as Hog
+import           Data.Foldable                  ( fold )
+import           Data.Functor.Foldable          ( cata )
+import qualified Data.Text                     as T
+import           Hedgehog                       ( Gen )
+import qualified Hedgehog.Gen                  as Hog
+import qualified Hedgehog.Range                as Hog
 import           VeriFuzz.Config
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index 8d19c14..16148cf 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -29,7 +29,7 @@ module VeriFuzz.Verilog.Internal
 where
 
 import           Control.Lens
-import           Data.Text            (Text)
+import           Data.Text                      ( Text )
 import           VeriFuzz.Verilog.AST
 
 regDecl :: Identifier -> ModItem
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 0fb4c49..e4a10df 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -41,10 +41,12 @@ module VeriFuzz.Verilog.Mutate
 where
 
 import           Control.Lens
-import           Data.Foldable             (fold)
-import           Data.Maybe                (catMaybes, fromMaybe)
-import           Data.Text                 (Text)
-import qualified Data.Text                 as T
+import           Data.Foldable                  ( fold )
+import           Data.Maybe                     ( catMaybes
+                                                , fromMaybe
+                                                )
+import           Data.Text                      ( Text )
+import qualified Data.Text                     as T
 import           VeriFuzz.Circuit.Internal
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
@@ -337,30 +339,30 @@ declareMod ports = initMod . (modItems %~ (decl ++))
 -- >>> GenVerilog . simplify $ (Id "y") + (Id "x")
 -- (y + x)
 simplify :: Expr -> Expr
-simplify (BinOp (Number (BitVec _ 1)) BinAnd e)   = e
-simplify (BinOp e BinAnd (Number (BitVec _ 1)))   = e
-simplify (BinOp (Number (BitVec _ 0)) BinAnd _)   = Number 0
-simplify (BinOp _ BinAnd (Number (BitVec _ 0)))   = Number 0
-simplify (BinOp e BinPlus (Number (BitVec _ 0)))  = e
-simplify (BinOp (Number (BitVec _ 0)) BinPlus e)  = e
+simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e
+simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0
+simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0
+simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e
 simplify (BinOp e BinMinus (Number (BitVec _ 0))) = e
 simplify (BinOp (Number (BitVec _ 0)) BinMinus e) = e
 simplify (BinOp e BinTimes (Number (BitVec _ 1))) = e
 simplify (BinOp (Number (BitVec _ 1)) BinTimes e) = e
 simplify (BinOp _ BinTimes (Number (BitVec _ 0))) = Number 0
 simplify (BinOp (Number (BitVec _ 0)) BinTimes _) = Number 0
-simplify (BinOp e BinOr (Number (BitVec _ 0)))    = e
-simplify (BinOp (Number (BitVec _ 0)) BinOr e)    = e
-simplify (BinOp e BinLSL (Number (BitVec _ 0)))   = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSL e)   = e
-simplify (BinOp e BinLSR (Number (BitVec _ 0)))   = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSR e)   = e
-simplify (BinOp e BinASL (Number (BitVec _ 0)))   = e
-simplify (BinOp (Number (BitVec _ 0)) BinASL e)   = e
-simplify (BinOp e BinASR (Number (BitVec _ 0)))   = e
-simplify (BinOp (Number (BitVec _ 0)) BinASR e)   = e
-simplify (UnOp UnPlus e)                          = e
-simplify e                                        = e
+simplify (BinOp e BinOr (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e
+simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e
+simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e
+simplify (BinOp e BinASL (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e
+simplify (BinOp e BinASR (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e
+simplify (UnOp UnPlus e) = e
+simplify e               = e
 
 -- | Remove all 'Identifier' that do not appeare in the input list from an
 -- 'Expr'. The identifier will be replaced by @1'b0@, which can then later be
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 68d0ef3..0820e48 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -26,17 +26,20 @@ module VeriFuzz.Verilog.Parser
 where
 
 import           Control.Lens
-import           Control.Monad               (void)
-import           Data.Bifunctor              (bimap)
+import           Control.Monad                  ( void )
+import           Data.Bifunctor                 ( bimap )
 import           Data.Bits
-import           Data.Functor                (($>))
-import           Data.Functor.Identity       (Identity)
-import           Data.List                   (isInfixOf, isPrefixOf, null)
-import           Data.List.NonEmpty          (NonEmpty (..))
-import           Data.Text                   (Text)
-import qualified Data.Text                   as T
-import qualified Data.Text.IO                as T
-import           Text.Parsec                 hiding (satisfy)
+import           Data.Functor                   ( ($>) )
+import           Data.Functor.Identity          ( Identity )
+import           Data.List                      ( isInfixOf
+                                                , isPrefixOf
+                                                , null
+                                                )
+import           Data.List.NonEmpty             ( NonEmpty(..) )
+import           Data.Text                      ( Text )
+import qualified Data.Text                     as T
+import qualified Data.Text.IO                  as T
+import           Text.Parsec             hiding ( satisfy )
 import           Text.Parsec.Expr
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs
index 362cf06..f0b7c96 100644
--- a/src/VeriFuzz/Verilog/Quote.hs
+++ b/src/VeriFuzz/Verilog/Quote.hs
@@ -18,8 +18,8 @@ module VeriFuzz.Verilog.Quote
 where
 
 import           Data.Data
-import qualified Data.Text                  as T
-import qualified Language.Haskell.TH        as TH
+import qualified Data.Text                     as T
+import qualified Language.Haskell.TH           as TH
 import           Language.Haskell.TH.Quote
 import           Language.Haskell.TH.Syntax
 import           VeriFuzz.Verilog.Parser
-- 
cgit