From 3f4cc4d325f740f7e70ad8ce02087fca41f79e31 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Thu, 4 Apr 2019 15:32:32 +0100
Subject: New combine function

---
 src/VeriFuzz/Verilog/Mutate.hs | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 69b6d57..eca472f 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -31,6 +31,7 @@ module VeriFuzz.Verilog.Mutate
     , simplify
     , removeId
     , combineAssigns
+    , combineAssigns_
     , declareMod
     )
 where
@@ -270,3 +271,7 @@ combineAssigns :: Port -> [ModItem] -> [ModItem]
 combineAssigns p a =
     a <> [ModCA . ContAssign (p ^. portName) . fold $ Id <$> assigns]
     where assigns = a ^.. traverse . modContAssign . contAssignNetLVal
+
+combineAssigns_ :: Port -> [Port] -> ModItem
+combineAssigns_ p ps =
+    ModCA . ContAssign (p ^. portName) . fold $ Id <$> ps ^.. traverse . portName
-- 
cgit