From 562f0da77e0464bfc21e8753070aec1cf9e60cf2 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 9 Jul 2019 22:02:45 +0200
Subject: Fix missing module instantiation

---
 src/VeriFuzz/Verilog/Gen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 3bfe4b9..2331068 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -362,7 +362,7 @@ instantiate :: ModDecl -> StateGen ModItem
 instantiate (ModDecl i outP inP _ _) = do
     context <- get
     outs    <- replicateM (length outP) (nextPort Wire)
-    ins <- take (length inP - 1) <$> Hog.shuffle (context ^. variables)
+    ins <- take (length inP) <$> Hog.shuffle (context ^. variables)
     sequence_ $ uncurry resizePort <$> zip (outs <> ins) (outP <> inP)
     ident <- makeIdentifier "modinst"
     Hog.choice
-- 
cgit