From 76ce30d979686307babe8ebb6269072338f24910 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Thu, 9 May 2019 18:54:43 +0100
Subject: Add reduction strategy for modules

---
 src/VeriFuzz/Verilog/AST.hs     | 9 ++++++---
 src/VeriFuzz/Verilog/CodeGen.hs | 2 +-
 src/VeriFuzz/Verilog/Mutate.hs  | 2 ++
 3 files changed, 9 insertions(+), 4 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index ea7ef1b..c4d889b 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -23,6 +23,8 @@ Defines the types to build a Verilog AST.
 module VeriFuzz.Verilog.AST
     ( -- * Top level types
       SourceInfo(..)
+    , infoTop
+    , infoSrc
     , Verilog(..)
     -- * Primitives
     -- ** Identifier
@@ -455,11 +457,11 @@ traverseModItem f (ModInst a b e) =
 traverseModItem _ e = pure e
 
 -- | The complete sourcetext for the Verilog module.
-newtype Verilog = Verilog { _getVerilog :: [ModDecl] }
+newtype Verilog = Verilog { getVerilog :: [ModDecl] }
                    deriving (Eq, Show, Ord, Data, Semigroup, Monoid)
 
-data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text
-                             , runSource     :: !Verilog
+data SourceInfo = SourceInfo { _infoTop :: {-# UNPACK #-} !Text
+                             , _infoSrc :: !Verilog
                              }
                   deriving (Eq, Show)
 
@@ -477,6 +479,7 @@ $(makeLenses ''ModItem)
 $(makeLenses ''Parameter)
 $(makeLenses ''LocalParam)
 $(makeLenses ''ModDecl)
+$(makeLenses ''SourceInfo)
 $(makeWrapped ''Verilog)
 $(makeWrapped ''Identifier)
 $(makeWrapped ''Delay)
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index f20d959..2531519 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -55,7 +55,7 @@ moduleDecl (ModDecl i outP inP items ps) =
         <> ports
         <> ";\n"
         <> modI
-        <> "endmodule\n"
+        <> "endmodule\n\n"
   where
     ports | null outP && null inP = ""
           | otherwise             = "(" <> comma (modPort <$> outIn) <> ")"
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 7b93633..e7b4874 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -123,6 +123,7 @@ allVars m =
 -- m m1(y, x);
 -- endmodule
 -- <BLANKLINE>
+-- <BLANKLINE>
 instantiateMod :: ModDecl -> ModDecl -> ModDecl
 instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
   where
@@ -184,6 +185,7 @@ filterChar t ids =
 -- input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
+-- <BLANKLINE>
 initMod :: ModDecl -> ModDecl
 initMod m = m & modItems %~ ((out ++ inp) ++)
   where
-- 
cgit