From 992e91427fccff43f8ab1944131b8f62f9328f0d Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 23 Jul 2019 22:05:32 +0200 Subject: Add new maintainer email --- src/VeriFuzz/Verilog/AST.hs | 18 +++++-------- src/VeriFuzz/Verilog/BitVec.hs | 2 +- src/VeriFuzz/Verilog/CodeGen.hs | 16 +++++------ src/VeriFuzz/Verilog/Eval.hs | 8 +++--- src/VeriFuzz/Verilog/Gen.hs | 24 ++++++++++------- src/VeriFuzz/Verilog/Internal.hs | 4 +-- src/VeriFuzz/Verilog/Mutate.hs | 55 ++++++++++++++++++-------------------- src/VeriFuzz/Verilog/Parser.hs | 25 ++++++++--------- src/VeriFuzz/Verilog/Preprocess.hs | 2 +- src/VeriFuzz/Verilog/Quote.hs | 6 ++--- src/VeriFuzz/Verilog/Token.hs | 2 +- 11 files changed, 78 insertions(+), 84 deletions(-) (limited to 'src/VeriFuzz/Verilog') diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 43063e6..e90d388 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.AST Description : Definition of the Verilog AST types. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Poratbility : POSIX @@ -139,18 +139,14 @@ module VeriFuzz.Verilog.AST ) where -import Control.Lens hiding ( (<|) ) +import Control.Lens hiding ((<|)) import Data.Data import Data.Data.Lens -import Data.Functor.Foldable.TH ( makeBaseFunctor ) -import Data.List.NonEmpty ( NonEmpty(..) - , (<|) - ) -import Data.String ( IsString - , fromString - ) -import Data.Text ( Text ) -import Data.Traversable ( sequenceA ) +import Data.Functor.Foldable.TH (makeBaseFunctor) +import Data.List.NonEmpty (NonEmpty (..), (<|)) +import Data.String (IsString, fromString) +import Data.Text (Text) +import Data.Traversable (sequenceA) import VeriFuzz.Verilog.BitVec -- | Identifier in Verilog. This is just a string of characters that can either diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs index cdae0f7..80fa539 100644 --- a/src/VeriFuzz/Verilog/BitVec.hs +++ b/src/VeriFuzz/Verilog/BitVec.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.BitVec Description : Unsigned BitVec implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 82945aa..56e2819 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.CodeGen Description : Code generation for Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -22,15 +22,13 @@ module VeriFuzz.Verilog.CodeGen ) where -import Data.Data ( Data ) -import Data.List.NonEmpty ( NonEmpty(..) - , toList - ) -import Data.Text ( Text ) -import qualified Data.Text as T +import Data.Data (Data) +import Data.List.NonEmpty (NonEmpty (..), toList) +import Data.Text (Text) +import qualified Data.Text as T import Data.Text.Prettyprint.Doc -import Numeric ( showHex ) -import VeriFuzz.Internal hiding ( comma ) +import Numeric (showHex) +import VeriFuzz.Internal hiding (comma) import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs index d8840e3..c802267 100644 --- a/src/VeriFuzz/Verilog/Eval.hs +++ b/src/VeriFuzz/Verilog/Eval.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Eval Description : Evaluation of Verilog expressions and statements. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -17,9 +17,9 @@ module VeriFuzz.Verilog.Eval where import Data.Bits -import Data.Foldable ( fold ) -import Data.Functor.Foldable hiding ( fold ) -import Data.Maybe ( listToMaybe ) +import Data.Foldable (fold) +import Data.Functor.Foldable hiding (fold) +import Data.Maybe (listToMaybe) import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 458878b..6cb6eb1 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Gen Description : Various useful generators. Copyright : (c) 2019, Yann Herklotz License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -30,7 +30,7 @@ import Control.Monad.Trans.Reader hiding (local) import Control.Monad.Trans.State.Strict import Data.Foldable (fold) import Data.Functor.Foldable (cata) -import Data.List (foldl') +import Data.List (foldl', partition) import qualified Data.Text as T import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog @@ -44,6 +44,7 @@ import VeriFuzz.Verilog.Internal import VeriFuzz.Verilog.Mutate -- Temporary imports +import Data.Char (toLower) import Debug.Trace import VeriFuzz.Verilog.CodeGen @@ -353,18 +354,23 @@ alwaysSeq = Always . EventCtrl (EPosEdge "clk") . Just <$> seqBlock resizePort :: [Parameter] -> Identifier -> Range -> [Port] -> [Port] resizePort ps i ra = foldl' func [] where - func l p@(Port _ _ ri i') - | i' == i && calc ri < calc ra = (p & portSize .~ ra) : l + func l p@(Port t _ ri i') + | i' == i && calc ri < calc ra = trace (fmap toLower (show t) <> " " <> show (GenVerilog i) <> ": " <> (show $ calc ri) <> " to " <> (show $ calc ra)) $ (p & portSize .~ ra) : l | otherwise = p : l calc = calcRange ps $ Just 64 -- | Instantiate a module, where the outputs are new nets that are created, and -- the inputs are taken from existing ports in the context. +-- +-- 1 is subtracted from the inputs for the length because the clock is not +-- counted and is assumed to be there, this should be made nicer by filtering +-- out the clock instead. I think that in general there should be a special +-- representation for the clock. instantiate :: ModDecl -> StateGen ModItem instantiate (ModDecl i outP inP _ _) = do context <- get outs <- replicateM (length outP) (nextPort Wire) - ins <- take (length inP) <$> Hog.shuffle (context ^. variables) + ins <- take (length inP - 1) <$> Hog.shuffle (context ^. variables) mapM_ (uncurry process) . zip (ins ^.. traverse . portName) $ inP ^.. traverse . portSize ident <- makeIdentifier "modinst" vs <- view variables <$> get @@ -466,8 +472,8 @@ calcRange ps i (Range l r) = eval l - eval r + 1 where eval a = fromIntegral . cata (evaluateConst ps) $ maybe a (`resize` a) i -notIdentElem :: Port -> [Port] -> Bool -notIdentElem p = notElem (p ^. portName) . toListOf (traverse . portName) +identElem :: Port -> [Port] -> Bool +identElem p = elem (p ^. portName) . toListOf (traverse . portName) -- | Generates a module definition randomly. It always has one output port which -- is set to @y@. The size of @y@ is the total combination of all the locally @@ -481,7 +487,7 @@ moduleDef top = do ps <- Hog.list (Hog.linear 0 10) parameter context <- get config <- lift ask - let local = filter (`notIdentElem` portList) $ _variables context + let (newPorts, local) = partition (`identElem` portList) $ _variables context let size = evalRange (_parameters context) 32 @@ -496,7 +502,7 @@ moduleDef top = do let comb = combineAssigns_ combine yport local return . declareMod local - . ModDecl name [yport] (clock : portList) (comb : mi) + . ModDecl name [yport] (clock : newPorts) (comb : mi) $ ps -- | Procedural generation method for random Verilog. Uses internal 'Reader' and diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs index 16148cf..42eb4e2 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/VeriFuzz/Verilog/Internal.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Internal Description : Defaults and common functions. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -29,7 +29,7 @@ module VeriFuzz.Verilog.Internal where import Control.Lens -import Data.Text ( Text ) +import Data.Text (Text) import VeriFuzz.Verilog.AST regDecl :: Identifier -> ModItem diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index e4a10df..37d3a7d 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Mutate Description : Functions to mutate the Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -41,12 +41,10 @@ module VeriFuzz.Verilog.Mutate where import Control.Lens -import Data.Foldable ( fold ) -import Data.Maybe ( catMaybes - , fromMaybe - ) -import Data.Text ( Text ) -import qualified Data.Text as T +import Data.Foldable (fold) +import Data.Maybe (catMaybes, fromMaybe) +import Data.Text (Text) +import qualified Data.Text as T import VeriFuzz.Circuit.Internal import VeriFuzz.Internal import VeriFuzz.Verilog.AST @@ -323,11 +321,10 @@ makeTopAssert = (modItems %~ (++ [assert])) . makeTop 2 -- | Provide declarations for all the ports that are passed to it. If they are -- registers, it should assign them to 0. declareMod :: [Port] -> ModDecl -> ModDecl -declareMod ports = initMod . (modItems %~ (decl ++)) +declareMod ports = initMod . (modItems %~ (fmap decl ports ++)) where - decl = declf <$> ports - declf p@(Port Reg _ _ _) = Decl Nothing p (Just 0) - declf p = Decl Nothing p Nothing + decl p@(Port Reg _ _ _) = Decl Nothing p (Just 0) + decl p = Decl Nothing p Nothing -- | Simplify an 'Expr' by using constants to remove 'BinaryOperator' and -- simplify expressions. To make this work effectively, it should be run until @@ -339,30 +336,30 @@ declareMod ports = initMod . (modItems %~ (decl ++)) -- >>> GenVerilog . simplify $ (Id "y") + (Id "x") -- (y + x) simplify :: Expr -> Expr -simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e -simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e -simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0 -simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0 -simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e +simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e +simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e +simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0 +simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0 +simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e simplify (BinOp e BinMinus (Number (BitVec _ 0))) = e simplify (BinOp (Number (BitVec _ 0)) BinMinus e) = e simplify (BinOp e BinTimes (Number (BitVec _ 1))) = e simplify (BinOp (Number (BitVec _ 1)) BinTimes e) = e simplify (BinOp _ BinTimes (Number (BitVec _ 0))) = Number 0 simplify (BinOp (Number (BitVec _ 0)) BinTimes _) = Number 0 -simplify (BinOp e BinOr (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e -simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e -simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e -simplify (BinOp e BinASL (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e -simplify (BinOp e BinASR (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e -simplify (UnOp UnPlus e) = e -simplify e = e +simplify (BinOp e BinOr (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e +simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e +simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e +simplify (BinOp e BinASL (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e +simplify (BinOp e BinASR (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e +simplify (UnOp UnPlus e) = e +simplify e = e -- | Remove all 'Identifier' that do not appeare in the input list from an -- 'Expr'. The identifier will be replaced by @1'b0@, which can then later be diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs index 0820e48..c08ebcd 100644 --- a/src/VeriFuzz/Verilog/Parser.hs +++ b/src/VeriFuzz/Verilog/Parser.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Parser Description : Minimal Verilog parser to reconstruct the AST. Copyright : (c) 2019, Yann Herklotz License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -26,20 +26,17 @@ module VeriFuzz.Verilog.Parser where import Control.Lens -import Control.Monad ( void ) -import Data.Bifunctor ( bimap ) +import Control.Monad (void) +import Data.Bifunctor (bimap) import Data.Bits -import Data.Functor ( ($>) ) -import Data.Functor.Identity ( Identity ) -import Data.List ( isInfixOf - , isPrefixOf - , null - ) -import Data.List.NonEmpty ( NonEmpty(..) ) -import Data.Text ( Text ) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Text.Parsec hiding ( satisfy ) +import Data.Functor (($>)) +import Data.Functor.Identity (Identity) +import Data.List (isInfixOf, isPrefixOf, null) +import Data.List.NonEmpty (NonEmpty (..)) +import Data.Text (Text) +import qualified Data.Text as T +import qualified Data.Text.IO as T +import Text.Parsec hiding (satisfy) import Text.Parsec.Expr import VeriFuzz.Internal import VeriFuzz.Verilog.AST diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/VeriFuzz/Verilog/Preprocess.hs index 6e9305a..c783ac5 100644 --- a/src/VeriFuzz/Verilog/Preprocess.hs +++ b/src/VeriFuzz/Verilog/Preprocess.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Preprocess Description : Simple preprocessor for `define and comments. Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs index f0b7c96..c6d3e3c 100644 --- a/src/VeriFuzz/Verilog/Quote.hs +++ b/src/VeriFuzz/Verilog/Quote.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Quote Description : QuasiQuotation for verilog code in Haskell. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -18,8 +18,8 @@ module VeriFuzz.Verilog.Quote where import Data.Data -import qualified Data.Text as T -import qualified Language.Haskell.TH as TH +import qualified Data.Text as T +import qualified Language.Haskell.TH as TH import Language.Haskell.TH.Quote import Language.Haskell.TH.Syntax import VeriFuzz.Verilog.Parser diff --git a/src/VeriFuzz/Verilog/Token.hs b/src/VeriFuzz/Verilog/Token.hs index 65c2319..d69f0b3 100644 --- a/src/VeriFuzz/Verilog/Token.hs +++ b/src/VeriFuzz/Verilog/Token.hs @@ -3,7 +3,7 @@ Module : VeriFuzz.Verilog.Token Description : Tokens for Verilog parsing. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX -- cgit