From cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 29 Aug 2019 15:44:33 +1000 Subject: Change name from VeriFuzz to VeriSmith --- src/VeriFuzz/Verilog/AST.hs | 6 +++--- src/VeriFuzz/Verilog/BitVec.hs | 4 ++-- src/VeriFuzz/Verilog/CodeGen.hs | 12 ++++++------ src/VeriFuzz/Verilog/Eval.hs | 14 +++++++------- src/VeriFuzz/Verilog/Internal.hs | 8 ++++---- src/VeriFuzz/Verilog/Lex.x | 4 ++-- src/VeriFuzz/Verilog/Mutate.hs | 28 ++++++++++++++-------------- src/VeriFuzz/Verilog/Parser.hs | 38 +++++++++++++++++++------------------- src/VeriFuzz/Verilog/Preprocess.hs | 4 ++-- src/VeriFuzz/Verilog/Quote.hs | 6 +++--- src/VeriFuzz/Verilog/Token.hs | 4 ++-- 11 files changed, 64 insertions(+), 64 deletions(-) (limited to 'src/VeriFuzz/Verilog') diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index a85c365..78bad45 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.AST +Module : VeriSmith.Verilog.AST Description : Definition of the Verilog AST types. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -22,7 +22,7 @@ Defines the types to build a Verilog AST. {-# LANGUAGE TemplateHaskell #-} {-# LANGUAGE TypeFamilies #-} -module VeriFuzz.Verilog.AST +module VeriSmith.Verilog.AST ( -- * Top level types SourceInfo(..) , infoTop @@ -150,7 +150,7 @@ import Data.String (IsString, fromString) import Data.Text (Text, pack) import Data.Traversable (sequenceA) import GHC.Generics (Generic) -import VeriFuzz.Verilog.BitVec +import VeriSmith.Verilog.BitVec -- | Identifier in Verilog. This is just a string of characters that can either -- be lowercase and uppercase for now. This might change in the future though, diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs index 0cc9eb3..dab9e2c 100644 --- a/src/VeriFuzz/Verilog/BitVec.hs +++ b/src/VeriFuzz/Verilog/BitVec.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.BitVec +Module : VeriSmith.Verilog.BitVec Description : Unsigned BitVec implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -17,7 +17,7 @@ Unsigned BitVec implementation. {-# LANGUAGE DeriveGeneric #-} {-# LANGUAGE DeriveTraversable #-} -module VeriFuzz.Verilog.BitVec +module VeriSmith.Verilog.BitVec ( BitVecF(..) , BitVec , bitVec diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 56e2819..1e94472 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.CodeGen +Module : VeriSmith.Verilog.CodeGen Description : Code generation for Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -8,13 +8,13 @@ Stability : experimental Portability : POSIX This module generates the code from the Verilog AST defined in -"VeriFuzz.Verilog.AST". +"VeriSmith.Verilog.AST". -} {-# LANGUAGE DeriveDataTypeable #-} {-# LANGUAGE FlexibleInstances #-} -module VeriFuzz.Verilog.CodeGen +module VeriSmith.Verilog.CodeGen ( -- * Code Generation GenVerilog(..) , Source(..) @@ -28,9 +28,9 @@ import Data.Text (Text) import qualified Data.Text as T import Data.Text.Prettyprint.Doc import Numeric (showHex) -import VeriFuzz.Internal hiding (comma) -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec +import VeriSmith.Internal hiding (comma) +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec -- | 'Source' class which determines that source code is able to be generated -- from the data structure using 'genSource'. This will be stored in 'Text' and diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs index c802267..1ebaa80 100644 --- a/src/VeriFuzz/Verilog/Eval.hs +++ b/src/VeriFuzz/Verilog/Eval.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Eval +Module : VeriSmith.Verilog.Eval Description : Evaluation of Verilog expressions and statements. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,18 +10,18 @@ Portability : POSIX Evaluation of Verilog expressions and statements. -} -module VeriFuzz.Verilog.Eval +module VeriSmith.Verilog.Eval ( evaluateConst , resize ) where import Data.Bits -import Data.Foldable (fold) -import Data.Functor.Foldable hiding (fold) -import Data.Maybe (listToMaybe) -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec +import Data.Foldable (fold) +import Data.Functor.Foldable hiding (fold) +import Data.Maybe (listToMaybe) +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec type Bindings = [Parameter] diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs index 42eb4e2..ed91b12 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/VeriFuzz/Verilog/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Internal +Module : VeriSmith.Verilog.Internal Description : Defaults and common functions. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Defaults and common functions. -} -module VeriFuzz.Verilog.Internal +module VeriSmith.Verilog.Internal ( regDecl , wireDecl , emptyMod @@ -29,8 +29,8 @@ module VeriFuzz.Verilog.Internal where import Control.Lens -import Data.Text (Text) -import VeriFuzz.Verilog.AST +import Data.Text (Text) +import VeriSmith.Verilog.AST regDecl :: Identifier -> ModItem regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing diff --git a/src/VeriFuzz/Verilog/Lex.x b/src/VeriFuzz/Verilog/Lex.x index cc67ecc..3d1dd8d 100644 --- a/src/VeriFuzz/Verilog/Lex.x +++ b/src/VeriFuzz/Verilog/Lex.x @@ -1,11 +1,11 @@ -- -*- haskell -*- { {-# OPTIONS_GHC -w #-} -module VeriFuzz.Verilog.Lex +module VeriSmith.Verilog.Lex ( alexScanTokens ) where -import VeriFuzz.Verilog.Token +import VeriSmith.Verilog.Token } diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 37d3a7d..58675e3 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Mutate +Module : VeriSmith.Verilog.Mutate Description : Functions to mutate the Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -7,13 +7,13 @@ Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX -Functions to mutate the Verilog AST from "VeriFuzz.Verilog.AST" to generate more +Functions to mutate the Verilog AST from "VeriSmith.Verilog.AST" to generate more random patterns, such as nesting wires instead of creating new ones. -} {-# LANGUAGE FlexibleInstances #-} -module VeriFuzz.Verilog.Mutate +module VeriSmith.Verilog.Mutate ( Mutate(..) , inPort , findAssign @@ -41,16 +41,16 @@ module VeriFuzz.Verilog.Mutate where import Control.Lens -import Data.Foldable (fold) -import Data.Maybe (catMaybes, fromMaybe) -import Data.Text (Text) -import qualified Data.Text as T -import VeriFuzz.Circuit.Internal -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Internal +import Data.Foldable (fold) +import Data.Maybe (catMaybes, fromMaybe) +import Data.Text (Text) +import qualified Data.Text as T +import VeriSmith.Circuit.Internal +import VeriSmith.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec +import VeriSmith.Verilog.CodeGen +import VeriSmith.Verilog.Internal class Mutate a where mutExpr :: (Expr -> Expr) -> a -> a @@ -210,7 +210,7 @@ allVars m = <> (m ^.. modInPorts . traverse . portName) -- $setup --- >>> import VeriFuzz.Verilog.CodeGen +-- >>> import VeriSmith.Verilog.CodeGen -- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [] []) -- >>> let main = (ModDecl "main" [] [] [] []) diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs index c08ebcd..8d2b729 100644 --- a/src/VeriFuzz/Verilog/Parser.hs +++ b/src/VeriFuzz/Verilog/Parser.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Parser +Module : VeriSmith.Verilog.Parser Description : Minimal Verilog parser to reconstruct the AST. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -11,7 +11,7 @@ Minimal Verilog parser to reconstruct the AST. This parser does not support the whole Verilog syntax, as the AST does not support it either. -} -module VeriFuzz.Verilog.Parser +module VeriSmith.Verilog.Parser ( -- * Parser parseVerilog , parseVerilogFile @@ -26,25 +26,25 @@ module VeriFuzz.Verilog.Parser where import Control.Lens -import Control.Monad (void) -import Data.Bifunctor (bimap) +import Control.Monad (void) +import Data.Bifunctor (bimap) import Data.Bits -import Data.Functor (($>)) -import Data.Functor.Identity (Identity) -import Data.List (isInfixOf, isPrefixOf, null) -import Data.List.NonEmpty (NonEmpty (..)) -import Data.Text (Text) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Text.Parsec hiding (satisfy) +import Data.Functor (($>)) +import Data.Functor.Identity (Identity) +import Data.List (isInfixOf, isPrefixOf, null) +import Data.List.NonEmpty (NonEmpty (..)) +import Data.Text (Text) +import qualified Data.Text as T +import qualified Data.Text.IO as T +import Text.Parsec hiding (satisfy) import Text.Parsec.Expr -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.Internal -import VeriFuzz.Verilog.Lex -import VeriFuzz.Verilog.Preprocess -import VeriFuzz.Verilog.Token +import VeriSmith.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec +import VeriSmith.Verilog.Internal +import VeriSmith.Verilog.Lex +import VeriSmith.Verilog.Preprocess +import VeriSmith.Verilog.Token type Parser = Parsec [Token] () diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/VeriFuzz/Verilog/Preprocess.hs index c783ac5..c30252b 100644 --- a/src/VeriFuzz/Verilog/Preprocess.hs +++ b/src/VeriFuzz/Verilog/Preprocess.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Preprocess +Module : VeriSmith.Verilog.Preprocess Description : Simple preprocessor for `define and comments. Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz License : GPL-3 @@ -14,7 +14,7 @@ The code is from https://github.com/tomahawkins/verilog. Edits to the original code are warning fixes and formatting changes. -} -module VeriFuzz.Verilog.Preprocess +module VeriSmith.Verilog.Preprocess ( uncomment , preprocess ) diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs index c6d3e3c..3815fe6 100644 --- a/src/VeriFuzz/Verilog/Quote.hs +++ b/src/VeriFuzz/Verilog/Quote.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Quote +Module : VeriSmith.Verilog.Quote Description : QuasiQuotation for verilog code in Haskell. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -12,7 +12,7 @@ QuasiQuotation for verilog code in Haskell. {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Verilog.Quote +module VeriSmith.Verilog.Quote ( verilog ) where @@ -22,7 +22,7 @@ import qualified Data.Text as T import qualified Language.Haskell.TH as TH import Language.Haskell.TH.Quote import Language.Haskell.TH.Syntax -import VeriFuzz.Verilog.Parser +import VeriSmith.Verilog.Parser liftDataWithText :: Data a => a -> Q Exp liftDataWithText = dataToExpQ $ fmap liftText . cast diff --git a/src/VeriFuzz/Verilog/Token.hs b/src/VeriFuzz/Verilog/Token.hs index d69f0b3..590672e 100644 --- a/src/VeriFuzz/Verilog/Token.hs +++ b/src/VeriFuzz/Verilog/Token.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Token +Module : VeriSmith.Verilog.Token Description : Tokens for Verilog parsing. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Tokens for Verilog parsing. -} -module VeriFuzz.Verilog.Token +module VeriSmith.Verilog.Token ( Token(..) , TokenName(..) , Position(..) -- cgit