From fe85c15c4a4dae8fa88f74472e6b42b31b17e2a1 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Thu, 10 Jan 2019 17:48:43 +0000
Subject: Add render to test

---
 src/VeriFuzz/Verilog/Mutate.hs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/VeriFuzz/Verilog')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 36cdb9b..e7bb199 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -87,7 +87,7 @@ allVars mod =
 -- it to the body of the second module. It first has to make all the inputs into
 -- @reg@.
 --
--- >>> instantiateMod mod main
+-- >>> render $ instantiateMod mod main
 -- module main;
 -- wire [4:0] y;
 -- reg [4:0] x;
@@ -107,7 +107,7 @@ instantiateMod mod main =
 -- | Instantiate without adding wire declarations. It also does not count the
 -- current instantiations of the same module.
 --
--- >>> instantiateMod_ mod
+-- >>> render $ instantiateMod_ mod
 -- m m(y, x);
 -- <BLANKLINE>
 instantiateMod_ :: ModDecl -> ModItem
@@ -119,7 +119,7 @@ instantiateMod_ mod =
 
 -- | Initialise all the inputs and outputs to a module.
 --
--- >>> initMod mod
+-- >>> render $ initMod mod
 -- module m(y, x);
 -- output wire [4:0] y;
 -- input wire [4:0] x;
-- 
cgit