From c0c799ab3f79c370e4c33b8f824489ce8b1c96ec Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Apr 2019 18:16:21 +0100 Subject: Rename to Verilog --- src/VeriFuzz/Yosys.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/VeriFuzz/Yosys.hs') diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index b6da8c2..ef2bc11 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -37,7 +37,7 @@ defaultYosys = Yosys "yosys" writeSimFile :: Yosys -- ^ Simulator instance - -> VerilogSrc -- ^ Current Verilog source + -> Verilog -- ^ Current Verilog source -> FilePath -- ^ Output sim file -> Sh () writeSimFile _ src file = do -- cgit