From 053be2bd7b06ecb371fa0e163d4d1c3e17fe0df3 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 15 Apr 2019 20:37:15 +0100 Subject: Move declaration of SourceInfo --- src/VeriFuzz/Fuzz.hs | 6 ++++-- src/VeriFuzz/Sim.hs | 5 ++--- src/VeriFuzz/Sim/Internal.hs | 20 -------------------- src/VeriFuzz/Sim/Quartus.hs | 1 + src/VeriFuzz/Sim/Reduce.hs | 1 - src/VeriFuzz/Sim/Vivado.hs | 1 + src/VeriFuzz/Sim/XST.hs | 1 + src/VeriFuzz/Sim/Yosys.hs | 1 + src/VeriFuzz/Verilog.hs | 3 ++- src/VeriFuzz/Verilog/AST.hs | 21 ++++++++++++++++++++- src/VeriFuzz/Verilog/CodeGen.hs | 1 - src/VeriFuzz/Verilog/Gen.hs | 13 +++++++------ 12 files changed, 39 insertions(+), 35 deletions(-) (limited to 'src/VeriFuzz') diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs index f0628e4..4c2b09a 100644 --- a/src/VeriFuzz/Fuzz.hs +++ b/src/VeriFuzz/Fuzz.hs @@ -36,6 +36,7 @@ import Control.Monad.IO.Class import Control.Monad.Trans.Class (lift) import Control.Monad.Trans.Reader hiding (local) import Control.Monad.Trans.State.Strict +import Hedgehog (Gen) import Prelude hiding (FilePath) import VeriFuzz.Sim.Icarus import VeriFuzz.Sim.Internal @@ -43,6 +44,7 @@ import VeriFuzz.Sim.Quartus import VeriFuzz.Sim.Vivado import VeriFuzz.Sim.XST import VeriFuzz.Sim.Yosys +import VeriFuzz.Verilog.AST data Result = Pass | EquivFail @@ -112,8 +114,8 @@ synthesisers = lift $ asks getSynthesisers simulators :: (Monad m) => Fuzz m [SimTool] simulators = lift $ asks getSimulators -fuzz :: (MonadIO m) => Fuzz m FuzzResult -fuzz = do +fuzz :: (MonadIO m) => Gen SourceInfo -> Fuzz m FuzzResult +fuzz _ = do _ <- synthesisers _ <- simulators return mempty diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs index f59271a..9ccbbd8 100644 --- a/src/VeriFuzz/Sim.hs +++ b/src/VeriFuzz/Sim.hs @@ -11,11 +11,10 @@ Simulator implementations. -} module VeriFuzz.Sim - ( -- * Environment - SourceInfo(..) + ( -- * Simulators -- ** Icarus - , Icarus(..) + Icarus(..) , defaultIcarus -- ** Yosys , Yosys(..) diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs index 3264d2e..3ff2924 100644 --- a/src/VeriFuzz/Sim/Internal.hs +++ b/src/VeriFuzz/Sim/Internal.hs @@ -14,8 +14,6 @@ module VeriFuzz.Sim.Internal ( Tool(..) , Simulator(..) , Synthesiser(..) - , SourceInfo(..) - , mainModule , rootPath , timeout , timeout_ @@ -27,7 +25,6 @@ module VeriFuzz.Sim.Internal ) where -import Control.Lens import Control.Monad (void) import Data.Bits (shiftL) import Data.ByteString (ByteString) @@ -63,23 +60,6 @@ class (Tool a) => Synthesiser a where -> FilePath -- ^ Output verilog file for the module -> Sh () -- ^ does not return any values -data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text - , runSource :: !Verilog - } - deriving (Eq, Show) - --- | May need to change this to Traversal to be safe. For now it will fail when --- the main has not been properly set with. -mainModule :: Lens' SourceInfo ModDecl -mainModule = lens get_ set_ - where - set_ (SourceInfo top main) v = - SourceInfo top (main & getModule %~ update top v) - update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v - | otherwise = m - get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule - f top (ModDecl (Identifier i) _ _ _ _) = i == top - rootPath :: Sh FilePath rootPath = do current <- pwd diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs index f0fbea9..13b27ae 100644 --- a/src/VeriFuzz/Sim/Quartus.hs +++ b/src/VeriFuzz/Sim/Quartus.hs @@ -19,6 +19,7 @@ where import Prelude hiding (FilePath) import Shelly import VeriFuzz.Sim.Internal +import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen newtype Quartus = Quartus { quartusBin :: Maybe FilePath } diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs index 3e3b1da..6dfe757 100644 --- a/src/VeriFuzz/Sim/Reduce.hs +++ b/src/VeriFuzz/Sim/Reduce.hs @@ -19,7 +19,6 @@ module VeriFuzz.Sim.Reduce where import Control.Lens -import VeriFuzz.Sim.Internal import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Mutate diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs index 99b102c..88328a6 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/VeriFuzz/Sim/Vivado.hs @@ -20,6 +20,7 @@ import Prelude hiding (FilePath) import Shelly import VeriFuzz.Sim.Internal import VeriFuzz.Sim.Template +import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen newtype Vivado = Vivado { vivadoPath :: FilePath } diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs index 59c897d..40bd637 100644 --- a/src/VeriFuzz/Sim/XST.hs +++ b/src/VeriFuzz/Sim/XST.hs @@ -23,6 +23,7 @@ import Shelly import Text.Shakespeare.Text (st) import VeriFuzz.Sim.Internal import VeriFuzz.Sim.Template +import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen data XST = XST { xstPath :: {-# UNPACK #-} !FilePath diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 4a68569..90a6ffd 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -26,6 +26,7 @@ import Shelly import Text.Shakespeare.Text (st) import VeriFuzz.Sim.Internal import VeriFuzz.Sim.Template +import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Mutate diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index dda3da1..ae4f82b 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -11,7 +11,8 @@ Verilog implementation with random generation and mutations. -} module VeriFuzz.Verilog - ( Verilog(..) + ( SourceInfo(..) + , Verilog(..) , parseVerilog , procedural , proceduralIO diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 3a4d2b9..0ef9057 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -22,7 +22,8 @@ Defines the types to build a Verilog AST. module VeriFuzz.Verilog.AST ( -- * Top level types - Verilog(..) + SourceInfo(..) + , Verilog(..) -- * Primitives -- ** Identifier , Identifier(..) @@ -127,6 +128,7 @@ module VeriFuzz.Verilog.AST -- * Useful Lenses and Traversals , getModule , getSourceId + , mainModule ) where @@ -452,6 +454,11 @@ traverseModItem _ e = pure e newtype Verilog = Verilog { _getVerilog :: [ModDecl] } deriving (Eq, Show, Ord, Data, Semigroup, Monoid) +data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text + , runSource :: !Verilog + } + deriving (Eq, Show) + $(makeLenses ''Expr) $(makeLenses ''ConstExpr) $(makeLenses ''Task) @@ -480,3 +487,15 @@ getModule = _Wrapped . traverse getSourceId :: Traversal' Verilog Text getSourceId = getModule . modId . _Wrapped {-# INLINE getSourceId #-} + +-- | May need to change this to Traversal to be safe. For now it will fail when +-- the main has not been properly set with. +mainModule :: Lens' SourceInfo ModDecl +mainModule = lens get_ set_ + where + set_ (SourceInfo top main) v = + SourceInfo top (main & getModule %~ update top v) + update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v + | otherwise = m + get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule + f top (ModDecl (Identifier i) _ _ _ _) = i == top diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 2030bc7..3b9c7ad 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -28,7 +28,6 @@ import qualified Data.Text as T import qualified Data.Text.IO as T import Numeric (showHex) import VeriFuzz.Internal -import VeriFuzz.Sim.Internal import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index a6ebbd9..46cdc25 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -436,10 +436,11 @@ moduleDef top = do -- | Procedural generation method for random Verilog. Uses internal 'Reader' and -- 'State' to keep track of the current Verilog code structure. -procedural :: Config -> Gen Verilog -procedural config = do - (mainMod, st) <- Hog.resize num - $ runReaderT (runStateT (moduleDef (Just "top")) context) config +procedural :: T.Text -> Config -> Gen Verilog +procedural top config = do + (mainMod, st) <- Hog.resize num $ runReaderT + (runStateT (moduleDef (Just $ Identifier top)) context) + config return . Verilog $ mainMod : st ^. modules where context = @@ -447,5 +448,5 @@ procedural config = do num = fromIntegral $ confProp propSize confProp i = config ^. configProperty . i -proceduralIO :: Config -> IO Verilog -proceduralIO = Hog.sample . procedural +proceduralIO :: T.Text -> Config -> IO Verilog +proceduralIO t = Hog.sample . procedural t -- cgit