From 52fd1a61b5491b877cd36123805144e5a635bda5 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Fri, 10 May 2019 17:42:03 +0100
Subject: Fix some of the doctests in Mutate.hs

---
 src/VeriFuzz/Verilog/Mutate.hs | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/VeriFuzz')

diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index e7b4874..35e0458 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -118,9 +118,9 @@ allVars m =
 --
 -- >>> render $ instantiateMod m main
 -- module main;
--- wire [(3'h4):(1'h0)] y;
--- reg [(3'h4):(1'h0)] x;
--- m m1(y, x);
+--   wire [(3'h4):(1'h0)] y;
+--   reg [(3'h4):(1'h0)] x;
+--   m m1(y, x);
 -- endmodule
 -- <BLANKLINE>
 -- <BLANKLINE>
@@ -181,8 +181,8 @@ filterChar t ids =
 --
 -- >>> GenVerilog $ initMod m
 -- module m(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 -- <BLANKLINE>
-- 
cgit