From 705bdb142b1088676ddc3178d8677bd40ab2b1d6 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Mon, 15 Apr 2019 19:50:49 +0100
Subject: Format with brittany and add right modules

---
 src/VeriFuzz/Fuzz.hs           |  3 ++-
 src/VeriFuzz/Sim.hs            |  2 +-
 src/VeriFuzz/Verilog/BitVec.hs | 10 +++++-----
 src/VeriFuzz/Verilog/Gen.hs    | 22 +++++++++++-----------
 4 files changed, 19 insertions(+), 18 deletions(-)

(limited to 'src/VeriFuzz')

diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs
index 1e48616..f0628e4 100644
--- a/src/VeriFuzz/Fuzz.hs
+++ b/src/VeriFuzz/Fuzz.hs
@@ -103,7 +103,8 @@ instance Monoid FuzzResult where
 type Fuzz m = StateT FuzzResult (ReaderT FuzzEnv m)
 
 runFuzz :: (Monad m) => [SynthTool] -> [SimTool] -> Fuzz m a -> m a
-runFuzz synth sim m =  runReaderT (evalStateT m (FuzzResult [] [])) (FuzzEnv synth sim)
+runFuzz synth sim m =
+    runReaderT (evalStateT m (FuzzResult [] [])) (FuzzEnv synth sim)
 
 synthesisers :: (Monad m) => Fuzz m [SynthTool]
 synthesisers = lift $ asks getSynthesisers
diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs
index 9dc21bd..f59271a 100644
--- a/src/VeriFuzz/Sim.hs
+++ b/src/VeriFuzz/Sim.hs
@@ -12,7 +12,7 @@ Simulator implementations.
 
 module VeriFuzz.Sim
     ( -- * Environment
-    SourceInfo(..)
+      SourceInfo(..)
     -- * Simulators
     -- ** Icarus
     , Icarus(..)
diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs
index 436af7b..cdae0f7 100644
--- a/src/VeriFuzz/Verilog/BitVec.hs
+++ b/src/VeriFuzz/Verilog/BitVec.hs
@@ -104,12 +104,12 @@ rotateBitVec b@(BitVec s _) n | n >= 0    = iterate rotateL1 b !! n
     testBits a b' n' = if testBit n' a then bit b' else zeroBits
 
 width' :: Integer -> Int
-width' a | a == 0 = 1
+width' a | a == 0    = 1
          | otherwise = width'' a
-    where
-        width'' a' | a' == 0    = 0
-                   | a' == -1   = 1
-                   | otherwise = 1 + width'' (shiftR a' 1)
+  where
+    width'' a' | a' == 0   = 0
+               | a' == -1  = 1
+               | otherwise = 1 + width'' (shiftR a' 1)
 
 both :: (a -> b) -> (a, a) -> (b, b)
 both f (a, b) = (f a, f b)
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 78e278e..a6ebbd9 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -20,17 +20,17 @@ module VeriFuzz.Verilog.Gen
     )
 where
 
-import           Control.Lens                   hiding (Context)
-import           Control.Monad                  (replicateM)
-import           Control.Monad.Trans.Class      (lift)
-import           Control.Monad.Trans.Reader     hiding (local)
-import           Control.Monad.Trans.State.Lazy
-import           Data.Foldable                  (fold)
-import           Data.List.NonEmpty             (toList)
-import qualified Data.Text                      as T
-import           Hedgehog                       (Gen)
-import qualified Hedgehog.Gen                   as Hog
-import qualified Hedgehog.Range                 as Hog
+import           Control.Lens                     hiding (Context)
+import           Control.Monad                    (replicateM)
+import           Control.Monad.Trans.Class        (lift)
+import           Control.Monad.Trans.Reader       hiding (local)
+import           Control.Monad.Trans.State.Strict
+import           Data.Foldable                    (fold)
+import           Data.List.NonEmpty               (toList)
+import qualified Data.Text                        as T
+import           Hedgehog                         (Gen)
+import qualified Hedgehog.Gen                     as Hog
+import qualified Hedgehog.Range                   as Hog
 import           VeriFuzz.Config
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
-- 
cgit