From 708e0b680a48e6eb21664a5f1de21815bebf91d2 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 19 Jan 2019 13:31:53 +0000 Subject: Small improvement to stmnt and expr function --- src/VeriFuzz/Verilog/AST.hs | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) (limited to 'src/VeriFuzz') diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 4c22e10..35f678f 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -221,13 +221,13 @@ instance IsString Expr where fromString = Str . fromString expr :: Int -> QC.Gen Expr -expr 0 = QC.oneof - [ Id <$> QC.arbitrary - , Number <$> positiveArb <*> QC.arbitrary - , UnOp <$> QC.arbitrary <*> QC.arbitrary - -- , Str <$> QC.arbitrary - ] expr n + | n == 0 = QC.oneof + [ Id <$> QC.arbitrary + , Number <$> positiveArb <*> QC.arbitrary + , UnOp <$> QC.arbitrary <*> QC.arbitrary + -- , Str <$> QC.arbitrary + ] | n > 0 = QC.oneof [ Id <$> QC.arbitrary , Number <$> positiveArb <*> QC.arbitrary @@ -293,6 +293,9 @@ instance QC.Arbitrary LVal where , RegSize <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary ] +instance IsString LVal where + fromString = RegId . fromString + -- | Different port direction that are supported in Verilog. data PortDir = PortIn -- ^ Input direction for port (@input@). | PortOut -- ^ Output direction for port (@output@). @@ -388,14 +391,14 @@ instance Monoid Stmnt where mempty = SeqBlock [] statement :: Int -> QC.Gen Stmnt -statement 0 = QC.oneof - [ BlockAssign <$> QC.arbitrary - , NonBlockAssign <$> QC.arbitrary - -- , StatCA <$> QC.arbitrary - , TaskEnable <$> QC.arbitrary - , SysTaskEnable <$> QC.arbitrary - ] statement n + | n == 0 = QC.oneof + [ BlockAssign <$> QC.arbitrary + , NonBlockAssign <$> QC.arbitrary + -- , StatCA <$> QC.arbitrary + , TaskEnable <$> QC.arbitrary + , SysTaskEnable <$> QC.arbitrary + ] | n > 0 = QC.oneof [ TimeCtrl <$> QC.arbitrary <*> (Just <$> substat 2) , SeqBlock <$> QC.listOf1 (substat 4) -- cgit