From 78e70ea4382af2ab093facda0657b7bd3fa2ff01 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 23 Apr 2019 13:33:52 +0100
Subject: Formatting files and add result type to front end

---
 src/VeriFuzz/Sim/Icarus.hs  |  2 +-
 src/VeriFuzz/Sim/Quartus.hs | 10 ++++++++--
 src/VeriFuzz/Sim/Vivado.hs  |  3 ++-
 src/VeriFuzz/Sim/Yosys.hs   |  3 +--
 4 files changed, 12 insertions(+), 6 deletions(-)

(limited to 'src/VeriFuzz')

diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index aceb516..ec79340 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -48,7 +48,7 @@ data Icarus = Icarus { icarusPath :: FilePath
               deriving (Eq)
 
 instance Show Icarus where
-    show _ = "show"
+    show _ = "iverilog"
 
 instance Tool Icarus where
   toText _ = "iverilog"
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index cac1fb8..0559637 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -54,8 +54,14 @@ runSynthQuartus sim (SourceInfo top src) = do
     ex (exec "quartus_fit") [top, "--part=5CGXFC7D6F31C6"]
     ex (exec "quartus_eda") [top, "--simulation", "--tool=vcs"]
     liftSh $ do
-        cp (fromText "simulation/vcs" </> fromText top <.> "vo") $ synthOutput sim
-        run_ "sed" ["-ri", "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;", toTextIgnore $ synthOutput sim]
+        cp (fromText "simulation/vcs" </> fromText top <.> "vo")
+            $ synthOutput sim
+        run_
+            "sed"
+            [ "-ri"
+            , "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;"
+            , toTextIgnore $ synthOutput sim
+            ]
         echoP "Quartus synthesis done"
   where
     inpf = "rtl.v"
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index d213a12..6ede8b5 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -47,7 +47,8 @@ runSynthVivado :: Vivado -> SourceInfo -> ResultSh ()
 runSynthVivado sim (SourceInfo top src) = do
     dir <- liftSh pwd
     liftSh $ do
-        writefile vivadoTcl . vivadoSynthConfig top . toTextIgnore $ synthOutput sim
+        writefile vivadoTcl . vivadoSynthConfig top . toTextIgnore $ synthOutput
+            sim
         writefile "rtl.v" $ genSource src
         run_ "sed" ["s/^module/(* use_dsp48=\"no\" *) module/;", "-i", "rtl.v"]
         echoP "Vivado: run"
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index f219e01..f72fb1a 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -66,8 +66,7 @@ runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do
     out  = toTextIgnore $ synthOutput sim
 
 runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> ResultSh ()
-runMaybeSynth (Just sim) srcInfo =
-    runSynth sim srcInfo
+runMaybeSynth (Just sim) srcInfo = runSynth sim srcInfo
 runMaybeSynth Nothing (SourceInfo _ src) =
     liftSh . writefile "rtl.v" $ genSource src
 
-- 
cgit