From 8109d52d387bd90052702a5a168ca9cf582766a0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 17 Apr 2019 11:01:59 +0100
Subject: Fix other type errors and replace with Result type

---
 src/VeriFuzz/Sim.hs       |  3 ---
 src/VeriFuzz/Sim/Yosys.hs | 57 +++++++++++++++++++++++++++--------------------
 2 files changed, 33 insertions(+), 27 deletions(-)

(limited to 'src/VeriFuzz')

diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs
index 9ccbbd8..b0905b7 100644
--- a/src/VeriFuzz/Sim.hs
+++ b/src/VeriFuzz/Sim.hs
@@ -25,8 +25,6 @@ module VeriFuzz.Sim
     -- ** XST
     , XST(..)
     , defaultXST
-    -- * Reducer
-    , reduce
     -- * Equivalence
     , runEquiv
     -- * Simulation
@@ -39,7 +37,6 @@ where
 
 import           VeriFuzz.Sim.Icarus
 import           VeriFuzz.Sim.Internal
-import           VeriFuzz.Sim.Reduce
 import           VeriFuzz.Sim.Vivado
 import           VeriFuzz.Sim.XST
 import           VeriFuzz.Sim.Yosys
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 90a6ffd..3e1754a 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -23,6 +23,7 @@ where
 import           Control.Lens
 import           Prelude                  hiding (FilePath)
 import           Shelly
+import           Shelly.Lifted            (liftSh)
 import           Text.Shakespeare.Text    (st)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
@@ -42,8 +43,8 @@ instance Synthesiser Yosys where
 defaultYosys :: Yosys
 defaultYosys = Yosys "yosys"
 
-runSynthYosys :: Yosys -> SourceInfo -> FilePath -> Sh ()
-runSynthYosys sim (SourceInfo _ src) outf = do
+runSynthYosys :: Yosys -> SourceInfo -> FilePath -> ResultSh ()
+runSynthYosys sim (SourceInfo _ src) outf = (<?> SynthFail) . liftSh $ do
     dir <- pwd
     writefile inpf $ genSource src
     echoP "Yosys: synthesis"
@@ -57,11 +58,11 @@ runSynthYosys sim (SourceInfo _ src) outf = do
     inp  = toTextIgnore inpf
     out  = toTextIgnore outf
 
-runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> Sh ()
+runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> ResultSh ()
 runMaybeSynth (Just sim) srcInfo =
     runSynth sim srcInfo $ fromText [st|syn_#{toText sim}.v|]
 runMaybeSynth Nothing (SourceInfo _ src) =
-    writefile "syn_rtl.v" $ genSource src
+    liftSh . writefile "syn_rtl.v" $ genSource src
 
 runEquivYosys
     :: (Synthesiser a, Synthesiser b)
@@ -69,15 +70,22 @@ runEquivYosys
     -> a
     -> Maybe b
     -> SourceInfo
-    -> Sh ()
+    -> ResultSh ()
 runEquivYosys yosys sim1 sim2 srcInfo = do
-    writefile "top.v" . genSource . initMod . makeTop 2 $ srcInfo ^. mainModule
-    writefile checkFile $ yosysSatConfig sim1 sim2 srcInfo
+    liftSh $ do
+        writefile "top.v"
+            .  genSource
+            .  initMod
+            .  makeTop 2
+            $  srcInfo
+            ^. mainModule
+        writefile checkFile $ yosysSatConfig sim1 sim2 srcInfo
     runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|]
     runMaybeSynth sim2 srcInfo
-    echoP "Yosys: equivalence check"
-    run_ (yosysPath yosys) [toTextIgnore checkFile]
-    echoP "Yosys: equivalence done"
+    liftSh $ do
+        echoP "Yosys: equivalence check"
+        run_ (yosysPath yosys) [toTextIgnore checkFile]
+        echoP "Yosys: equivalence done"
   where
     checkFile =
         fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
@@ -88,20 +96,21 @@ runEquiv
     -> a
     -> Maybe b
     -> SourceInfo
-    -> Sh ()
+    -> ResultSh ()
 runEquiv _ sim1 sim2 srcInfo = do
-    root <- rootPath
-    dir  <- pwd
-    echoP "SymbiYosys: setup"
-    writefile "top.v"
-        .  genSource
-        .  initMod
-        .  makeTopAssert
-        $  srcInfo
-        ^. mainModule
-    writefile "test.sby" $ sbyConfig root sim1 sim2 srcInfo
+    root <- liftSh rootPath
+    dir  <- liftSh pwd
+    liftSh $ do
+        echoP "SymbiYosys: setup"
+        writefile "top.v"
+            .  genSource
+            .  initMod
+            .  makeTopAssert
+            $  srcInfo
+            ^. mainModule
+        writefile "test.sby" $ sbyConfig root sim1 sim2 srcInfo
     runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|]
     runMaybeSynth sim2 srcInfo
-    echoP "SymbiYosys: run"
-    logger_ dir "symbiyosys" $ run "sby" ["-f", "test.sby"]
-    echoP "SymbiYosys: done"
+    liftSh $ echoP "SymbiYosys: run"
+    execute_ EquivFail dir "symbiyosys" "sby" ["-f", "test.sby"]
+    liftSh $ echoP "SymbiYosys: done"
-- 
cgit