From 8241ebad9374187b20ee0fdd43029a2a5ddfbb4e Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Fri, 10 May 2019 17:40:57 +0100
Subject: Fix but remove the doctests for now

They were not working well with the current printing method. I have to find a
way to remove the spaces from the output.
---
 src/VeriFuzz/Reduce.hs | 50 +++++++++++++++++++++++++-------------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

(limited to 'src/VeriFuzz')

diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index 48a3c78..df92d99 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -188,14 +188,14 @@ halveExpr = combine contexpr $ traverse halveModExpr
 --
 -- >>> GenVerilog srcInfo
 -- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m m(y, x);
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
+--   m m(y, x);
 -- endmodule
 -- <BLANKLINE>
 -- module m(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 -- <BLANKLINE>
@@ -203,28 +203,28 @@ halveExpr = combine contexpr $ traverse halveModExpr
 -- >>> GenVerilog <$> halveModules srcInfo
 -- --- Only try:
 -- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 -- <BLANKLINE>
 --
 -- >>> GenVerilog srcInfo2
 -- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m m(y, x);
--- m2 m2(y, x);
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
+--   m m(y, x);
+--   m2 m2(y, x);
 -- endmodule
 -- <BLANKLINE>
 -- module m(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 -- module m2(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 -- <BLANKLINE>
@@ -232,27 +232,27 @@ halveExpr = combine contexpr $ traverse halveModExpr
 -- >>> GenVerilog <$> halveModules srcInfo2
 -- --- Try:
 -- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m m(y, x);
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
+--   m m(y, x);
 -- endmodule
 -- <BLANKLINE>
 -- module m(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 -- <BLANKLINE>
 -- --- Then:
 -- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m2 m2(y, x);
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
+--   m2 m2(y, x);
 -- endmodule
 -- <BLANKLINE>
 -- module m2(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+--   output wire [(3'h4):(1'h0)] y;
+--   input wire [(3'h4):(1'h0)] x;
 -- endmodule
 -- <BLANKLINE>
 -- <BLANKLINE>
-- 
cgit