From ad5d8bced5aec1e887c44e7e3c26a9b74c5a3ba5 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 2 Feb 2019 22:54:27 +0000 Subject: Add timeout and timeout check --- src/VeriFuzz/Yosys.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/VeriFuzz') diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index e64104a..d7b0014 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -48,7 +48,7 @@ runSynthYosys sim m outf = do dir <- pwd writefile inpf $ genSource m echoP "Yosys: synthesis" - _ <- logger dir "yosys" $ run (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] + _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] echoP "Yosys: synthesis done" where inpf = "rtl.v" -- cgit