From a2b01b92612a098673ff03890e6e8aef4ceb28ea Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 4 Sep 2019 20:15:51 +1000
Subject: Renaming to VeriSmith

---
 src/VeriSmith/Circuit.hs | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 src/VeriSmith/Circuit.hs

(limited to 'src/VeriSmith/Circuit.hs')

diff --git a/src/VeriSmith/Circuit.hs b/src/VeriSmith/Circuit.hs
new file mode 100644
index 0000000..aee0d57
--- /dev/null
+++ b/src/VeriSmith/Circuit.hs
@@ -0,0 +1,45 @@
+{-|
+Module      : VeriSmith.Circuit
+Description : Definition of the circuit graph.
+Copyright   : (c) 2018-2019, Yann Herklotz
+License     : BSD-3
+Maintainer  : yann [at] yannherklotz [dot] com
+Stability   : experimental
+Portability : POSIX
+
+Definition of the circuit graph.
+-}
+
+module VeriSmith.Circuit
+    ( -- * Circuit
+      Gate(..)
+    , Circuit(..)
+    , CNode(..)
+    , CEdge(..)
+    , fromGraph
+    , generateAST
+    , rDups
+    , rDupsCirc
+    , randomDAG
+    , genRandomDAG
+    )
+where
+
+import           Control.Lens
+import           Hedgehog                 (Gen)
+import qualified Hedgehog.Gen             as Hog
+import           VeriSmith.Circuit.Base
+import           VeriSmith.Circuit.Gen
+import           VeriSmith.Circuit.Random
+import           VeriSmith.Verilog.AST
+import           VeriSmith.Verilog.Mutate
+
+fromGraph :: Gen ModDecl
+fromGraph = do
+    gr <- rDupsCirc <$> Hog.resize 100 randomDAG
+    return
+        $   initMod
+        .   head
+        $   nestUpTo 5 (generateAST gr)
+        ^.. _Wrapped
+        .   traverse
-- 
cgit