From 8d96fd2a541a2602544ced741552ebd17714c67d Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 18 Sep 2019 19:06:32 +0200
Subject: Rename main modules

---
 src/VeriSmith/Sim/XST.hs | 85 ------------------------------------------------
 1 file changed, 85 deletions(-)
 delete mode 100644 src/VeriSmith/Sim/XST.hs

(limited to 'src/VeriSmith/Sim/XST.hs')

diff --git a/src/VeriSmith/Sim/XST.hs b/src/VeriSmith/Sim/XST.hs
deleted file mode 100644
index 30a4b0b..0000000
--- a/src/VeriSmith/Sim/XST.hs
+++ /dev/null
@@ -1,85 +0,0 @@
-{-|
-Module      : VeriSmith.Sim.XST
-Description : XST (ise) simulator implementation.
-Copyright   : (c) 2018-2019, Yann Herklotz
-License     : BSD-3
-Maintainer  : yann [at] yannherklotz [dot] com
-Stability   : experimental
-Portability : POSIX
-
-XST (ise) simulator implementation.
--}
-
-{-# LANGUAGE QuasiQuotes #-}
-
-module VeriSmith.Sim.XST
-    ( XST(..)
-    , defaultXST
-    )
-where
-
-import           Control.DeepSeq           (NFData, rnf, rwhnf)
-import           Data.Text                 (Text, unpack)
-import           Prelude                   hiding (FilePath)
-import           Shelly
-import           Shelly.Lifted             (liftSh)
-import           Text.Shakespeare.Text     (st)
-import           VeriSmith.Sim.Internal
-import           VeriSmith.Sim.Template
-import           VeriSmith.Verilog.AST
-import           VeriSmith.Verilog.CodeGen
-
-data XST = XST { xstBin    :: !(Maybe FilePath)
-               , xstDesc   :: {-# UNPACK #-} !Text
-               , xstOutput :: {-# UNPACK #-} !FilePath
-               }
-         deriving (Eq)
-
-instance Tool XST where
-    toText (XST _ t _) = t
-
-instance Show XST where
-    show t = unpack $ toText t
-
-instance Synthesiser XST where
-    runSynth = runSynthXST
-    synthOutput = xstOutput
-    setSynthOutput (XST a b _) = XST a b
-
-instance NFData XST where
-    rnf = rwhnf
-
-defaultXST :: XST
-defaultXST = XST Nothing "xst" "syn_xst.v"
-
-runSynthXST :: XST -> SourceInfo -> ResultSh ()
-runSynthXST sim (SourceInfo top src) = do
-    dir <- liftSh pwd
-    let exec n = execute_
-            SynthFail
-            dir
-            "xst"
-            (maybe (fromText n) (</> fromText n) $ xstBin sim)
-    liftSh $ do
-        writefile xstFile $ xstSynthConfig top
-        writefile prjFile [st|verilog work "rtl.v"|]
-        writefile "rtl.v" $ genSource src
-    exec "xst" ["-ifn", toTextIgnore xstFile]
-    exec
-        "netgen"
-        [ "-w"
-        , "-ofmt"
-        , "verilog"
-        , toTextIgnore $ modFile <.> "ngc"
-        , toTextIgnore $ synthOutput sim
-        ]
-    liftSh . noPrint $ run_
-        "sed"
-        [ "-i"
-        , "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;"
-        , toTextIgnore $ synthOutput sim
-        ]
-  where
-    modFile = fromText top
-    xstFile = modFile <.> "xst"
-    prjFile = modFile <.> "prj"
-- 
cgit