From 8d96fd2a541a2602544ced741552ebd17714c67d Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 18 Sep 2019 19:06:32 +0200
Subject: Rename main modules

---
 src/VeriSmith/Verilog.hs | 106 -----------------------------------------------
 1 file changed, 106 deletions(-)
 delete mode 100644 src/VeriSmith/Verilog.hs

(limited to 'src/VeriSmith/Verilog.hs')

diff --git a/src/VeriSmith/Verilog.hs b/src/VeriSmith/Verilog.hs
deleted file mode 100644
index 6e7851c..0000000
--- a/src/VeriSmith/Verilog.hs
+++ /dev/null
@@ -1,106 +0,0 @@
-{-|
-Module      : VeriSmith.Verilog
-Description : Verilog implementation with random generation and mutations.
-Copyright   : (c) 2019, Yann Herklotz Grave
-License     : GPL-3
-Maintainer  : yann [at] yannherklotz [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Verilog implementation with random generation and mutations.
--}
-
-{-# LANGUAGE QuasiQuotes #-}
-
-module VeriSmith.Verilog
-    ( SourceInfo(..)
-    , Verilog(..)
-    , parseVerilog
-    , GenVerilog(..)
-    , genSource
-    -- * Primitives
-    -- ** Identifier
-    , Identifier(..)
-    -- ** Control
-    , Delay(..)
-    , Event(..)
-    -- ** Operators
-    , BinaryOperator(..)
-    , UnaryOperator(..)
-    -- ** Task
-    , Task(..)
-    , taskName
-    , taskExpr
-    -- ** Left hand side value
-    , LVal(..)
-    , regId
-    , regExprId
-    , regExpr
-    , regSizeId
-    , regSizeRange
-    , regConc
-    -- ** Ports
-    , PortDir(..)
-    , PortType(..)
-    , Port(..)
-    , portType
-    , portSigned
-    , portSize
-    , portName
-    -- * Expression
-    , Expr(..)
-    , ConstExpr(..)
-    , constToExpr
-    , exprToConst
-    , constNum
-    -- * Assignment
-    , Assign(..)
-    , assignReg
-    , assignDelay
-    , assignExpr
-    , ContAssign(..)
-    , contAssignNetLVal
-    , contAssignExpr
-    -- * Statment
-    , Statement(..)
-    , statDelay
-    , statDStat
-    , statEvent
-    , statEStat
-    , statements
-    , stmntBA
-    , stmntNBA
-    , stmntTask
-    , stmntSysTask
-    , stmntCondExpr
-    , stmntCondTrue
-    , stmntCondFalse
-    -- * Module
-    , ModDecl(..)
-    , modId
-    , modOutPorts
-    , modInPorts
-    , modItems
-    , ModItem(..)
-    , modContAssign
-    , modInstId
-    , modInstName
-    , modInstConns
-    , traverseModItem
-    , declDir
-    , declPort
-    , ModConn(..)
-    , modConnName
-    , modExpr
-    -- * Useful Lenses and Traversals
-    , getModule
-    , getSourceId
-    -- * Quote
-    , verilog
-    )
-where
-
-import           VeriSmith.Verilog.AST
-import           VeriSmith.Verilog.CodeGen
-import           VeriSmith.Verilog.Parser
-import           VeriSmith.Verilog.Quote
-- 
cgit