From e7f57642f068650ea362201b239efad1c9a841d9 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 18 Oct 2019 14:29:07 +0100
Subject: Rename Sim to Tool

---
 src/Verismith.hs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/Verismith.hs')

diff --git a/src/Verismith.hs b/src/Verismith.hs
index e7d3ce6..85deca3 100644
--- a/src/Verismith.hs
+++ b/src/Verismith.hs
@@ -30,7 +30,7 @@ module Verismith
     , module Verismith.Verilog
     , module Verismith.Config
     , module Verismith.Circuit
-    , module Verismith.Sim
+    , module Verismith.Tool
     , module Verismith.Fuzz
     , module Verismith.Report
     )
@@ -65,8 +65,8 @@ import           Verismith.Generate
 import           Verismith.Reduce
 import           Verismith.Report
 import           Verismith.Result
-import           Verismith.Sim
-import           Verismith.Sim.Internal
+import           Verismith.Tool
+import           Verismith.Tool.Internal
 import           Verismith.Verilog
 import           Verismith.Verilog.Parser (parseSourceInfoFile)
 
-- 
cgit