From 7124a4f00e536b4d5323a7488c1f65469dddb102 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 12 May 2020 12:21:36 +0100
Subject: Format with ormolu

---
 src/Verismith/Circuit/Gen.hs | 60 +++++++++++++++++++++-----------------------
 1 file changed, 29 insertions(+), 31 deletions(-)

(limited to 'src/Verismith/Circuit/Gen.hs')

diff --git a/src/Verismith/Circuit/Gen.hs b/src/Verismith/Circuit/Gen.hs
index 07b6c06..7b3f072 100644
--- a/src/Verismith/Circuit/Gen.hs
+++ b/src/Verismith/Circuit/Gen.hs
@@ -1,27 +1,25 @@
-{-|
-Module      : Verilog.Circuit.Gen
-Description : Generate verilog from circuit.
-Copyright   : (c) 2019, Yann Herklotz Grave
-License     : GPL-3
-Maintainer  : yann [at] yannherklotz [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Generate verilog from circuit.
--}
-
+-- |
+-- Module      : Verilog.Circuit.Gen
+-- Description : Generate verilog from circuit.
+-- Copyright   : (c) 2019, Yann Herklotz Grave
+-- License     : GPL-3
+-- Maintainer  : yann [at] yannherklotz [dot] com
+-- Stability   : experimental
+-- Portability : POSIX
+--
+-- Generate verilog from circuit.
 module Verismith.Circuit.Gen
-    ( generateAST
-    )
+  ( generateAST,
+  )
 where
 
-import           Data.Graph.Inductive       (LNode, Node)
-import qualified Data.Graph.Inductive       as G
-import           Data.Maybe                 (catMaybes)
-import           Verismith.Circuit.Base
-import           Verismith.Circuit.Internal
-import           Verismith.Verilog.AST
-import           Verismith.Verilog.Mutate
+import Data.Graph.Inductive (LNode, Node)
+import qualified Data.Graph.Inductive as G
+import Data.Maybe (catMaybes)
+import Verismith.Circuit.Base
+import Verismith.Circuit.Internal
+import Verismith.Verilog.AST
+import Verismith.Verilog.Mutate
 
 -- | Converts a 'CNode' to an 'Identifier'.
 frNode :: Node -> Identifier
@@ -31,7 +29,7 @@ frNode = Identifier . fromNode
 -- mapping.
 fromGate :: Gate -> BinaryOperator
 fromGate And = BinAnd
-fromGate Or  = BinOr
+fromGate Or = BinOr
 fromGate Xor = BinXor
 
 inputsC :: Circuit -> [Node]
@@ -43,8 +41,8 @@ genPortsAST f c = port . frNode <$> f c where port = Port Wire False 4
 -- | Generates the nested expression AST, so that it can then generate the
 -- assignment expressions.
 genAssignExpr :: Gate -> [Node] -> Maybe Expr
-genAssignExpr _ []       = Nothing
-genAssignExpr _ [n     ] = Just . Id $ frNode n
+genAssignExpr _ [] = Nothing
+genAssignExpr _ [n] = Just . Id $ frNode n
 genAssignExpr g (n : ns) = BinOp wire oper <$> genAssignExpr g ns
   where
     wire = Id $ frNode n
@@ -56,24 +54,24 @@ genAssignExpr g (n : ns) = BinOp wire oper <$> genAssignExpr g ns
 genContAssignAST :: Circuit -> LNode Gate -> Maybe (ModItem ann)
 genContAssignAST c (n, g) = ModCA . ContAssign name <$> genAssignExpr g nodes
   where
-    gr    = getCircuit c
+    gr = getCircuit c
     nodes = G.pre gr n
-    name  = frNode n
+    name = frNode n
 
 genAssignAST :: Circuit -> [ModItem ann]
 genAssignAST c = catMaybes $ genContAssignAST c <$> nodes
   where
-    gr    = getCircuit c
+    gr = getCircuit c
     nodes = G.labNodes gr
 
 genModuleDeclAST :: Circuit -> (ModDecl ann)
 genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) []
   where
-    i      = Identifier "gen_module"
-    ports  = genPortsAST inputsC c
+    i = Identifier "gen_module"
+    ports = genPortsAST inputsC c
     output = []
-    a      = genAssignAST c
-    yPort  = Port Wire False 90 "y"
+    a = genAssignAST c
+    yPort = Port Wire False 90 "y"
 
 generateAST :: Circuit -> (Verilog ann)
 generateAST c = Verilog [genModuleDeclAST c]
-- 
cgit