From 805f67c07cc15d784078b00a84f4055f84016cec Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 11 May 2020 18:29:06 +0100 Subject: Fix types with annotations --- src/Verismith/Tool/QuartusLight.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/Verismith/Tool/QuartusLight.hs') diff --git a/src/Verismith/Tool/QuartusLight.hs b/src/Verismith/Tool/QuartusLight.hs index f703da0..cdf2636 100644 --- a/src/Verismith/Tool/QuartusLight.hs +++ b/src/Verismith/Tool/QuartusLight.hs @@ -49,7 +49,7 @@ instance NFData QuartusLight where defaultQuartusLight :: QuartusLight defaultQuartusLight = QuartusLight Nothing "quartus" "syn_quartus.v" -runSynthQuartusLight :: QuartusLight -> (SourceInfo ann) -> ResultSh () +runSynthQuartusLight :: Show ann => QuartusLight -> (SourceInfo ann) -> ResultSh () runSynthQuartusLight sim (SourceInfo top src) = do dir <- liftSh pwd let ex = execute_ SynthFail dir "quartus" -- cgit From 7124a4f00e536b4d5323a7488c1f65469dddb102 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 12 May 2020 12:21:36 +0100 Subject: Format with ormolu --- src/Verismith/Tool/QuartusLight.hs | 113 +++++++++++++++++++------------------ 1 file changed, 58 insertions(+), 55 deletions(-) (limited to 'src/Verismith/Tool/QuartusLight.hs') diff --git a/src/Verismith/Tool/QuartusLight.hs b/src/Verismith/Tool/QuartusLight.hs index cdf2636..cab1087 100644 --- a/src/Verismith/Tool/QuartusLight.hs +++ b/src/Verismith/Tool/QuartusLight.hs @@ -1,76 +1,79 @@ -{-| -Module : Verismith.Tool.QuartusLight -Description : QuartusLight synthesiser implementation. -Copyright : (c) 2019, Yann Herklotz Grave -License : GPL-3 -Maintainer : yann [at] yannherklotz [dot] com -Stability : experimental -Portability : POSIX - -QuartusLight synthesiser implementation. --} - +-- | +-- Module : Verismith.Tool.QuartusLight +-- Description : QuartusLight synthesiser implementation. +-- Copyright : (c) 2019, Yann Herklotz Grave +-- License : GPL-3 +-- Maintainer : yann [at] yannherklotz [dot] com +-- Stability : experimental +-- Portability : POSIX +-- +-- QuartusLight synthesiser implementation. module Verismith.Tool.QuartusLight - ( QuartusLight(..) - , defaultQuartusLight - ) + ( QuartusLight (..), + defaultQuartusLight, + ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) -import Shelly -import Shelly.Lifted (liftSh) -import Verismith.Tool.Internal -import Verismith.Tool.Template -import Verismith.Verilog.AST -import Verismith.Verilog.CodeGen +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Shelly +import Shelly.Lifted (liftSh) +import Verismith.Tool.Internal +import Verismith.Tool.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen +import Prelude hiding (FilePath) -data QuartusLight = QuartusLight { quartusLightBin :: !(Maybe FilePath) - , quartusLightDesc :: !Text - , quartusLightOutput :: !FilePath - } - deriving (Eq) +data QuartusLight + = QuartusLight + { quartusLightBin :: !(Maybe FilePath), + quartusLightDesc :: !Text, + quartusLightOutput :: !FilePath + } + deriving (Eq) instance Tool QuartusLight where - toText (QuartusLight _ t _) = t + toText (QuartusLight _ t _) = t instance Show QuartusLight where - show t = unpack $ toText t + show t = unpack $ toText t instance Synthesiser QuartusLight where - runSynth = runSynthQuartusLight - synthOutput = quartusLightOutput - setSynthOutput (QuartusLight a b _) = QuartusLight a b + runSynth = runSynthQuartusLight + synthOutput = quartusLightOutput + setSynthOutput (QuartusLight a b _) = QuartusLight a b instance NFData QuartusLight where - rnf = rwhnf + rnf = rwhnf defaultQuartusLight :: QuartusLight defaultQuartusLight = QuartusLight Nothing "quartus" "syn_quartus.v" runSynthQuartusLight :: Show ann => QuartusLight -> (SourceInfo ann) -> ResultSh () runSynthQuartusLight sim (SourceInfo top src) = do - dir <- liftSh pwd - let ex = execute_ SynthFail dir "quartus" - liftSh $ do - writefile inpf $ genSource src - noPrint $ run_ "sed" [ "-i" - , "s/^module/(* multstyle = \"logic\" *) module/;" - , toTextIgnore inpf - ] - writefile quartusSdc "create_clock -period 5 -name clk [get_ports clock]" - writefile quartusTcl $ quartusLightSynthConfig sim quartusSdc top inpf - ex (exec "quartus_sh") ["-t", toTextIgnore quartusTcl] - liftSh $ do - cp (fromText "simulation/vcs" fromText top <.> "vo") - $ synthOutput sim - run_ - "sed" - [ "-ri" - , "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;" - , toTextIgnore $ synthOutput sim - ] + dir <- liftSh pwd + let ex = execute_ SynthFail dir "quartus" + liftSh $ do + writefile inpf $ genSource src + noPrint $ + run_ + "sed" + [ "-i", + "s/^module/(* multstyle = \"logic\" *) module/;", + toTextIgnore inpf + ] + writefile quartusSdc "create_clock -period 5 -name clk [get_ports clock]" + writefile quartusTcl $ quartusLightSynthConfig sim quartusSdc top inpf + ex (exec "quartus_sh") ["-t", toTextIgnore quartusTcl] + liftSh $ do + cp (fromText "simulation/vcs" fromText top <.> "vo") $ + synthOutput sim + run_ + "sed" + [ "-ri", + "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;", + toTextIgnore $ synthOutput sim + ] where inpf = "rtl.v" exec s = maybe (fromText s) ( fromText s) $ quartusLightBin sim -- cgit