From 472aedf5daeb1cb0d095a63eacf259b798f56586 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Mon, 16 Mar 2020 13:12:30 +0000
Subject: WIP changes to the AST types

---
 src/Verismith/Tool/Template.hs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/Verismith/Tool/Template.hs')

diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs
index ffa7240..ad9860c 100644
--- a/src/Verismith/Tool/Template.hs
+++ b/src/Verismith/Tool/Template.hs
@@ -61,7 +61,7 @@ write_verilog #{outputText a}
 yosysSynthConfigStd :: Synthesiser a => a -> FilePath -> Text
 yosysSynthConfigStd = yosysSynthConfig "synth"
 
-yosysSatConfig :: (Synthesiser a, Synthesiser b) => a -> b -> SourceInfo -> Text
+yosysSatConfig :: (Synthesiser a, Synthesiser b) => a -> b -> (SourceInfo ann) -> Text
 yosysSatConfig sim1 sim2 (SourceInfo top src) = [st|read_verilog #{outputText sim1}
 #{rename "_1" mis}
 read_verilog syn_#{outputText sim2}.v
@@ -137,7 +137,7 @@ synth_design -part xc7k70t -top #{top}
 write_verilog -force #{outf}
 |]
 
-sbyConfig :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> SourceInfo -> Text
+sbyConfig :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> (SourceInfo ann) -> Text
 sbyConfig mt datadir sim1 sim2 (SourceInfo top _) = [st|[options]
 multiclock on
 mode prove
@@ -169,7 +169,7 @@ top.v
         <$> deps
     readL = T.intercalate "\n" $ mappend "read -formal " <$> deps
 
-icarusTestbench :: (Synthesiser a) => FilePath -> Verilog -> a -> Text
+icarusTestbench :: (Synthesiser a) => FilePath -> (Verilog ann) -> a -> Text
 icarusTestbench datadir t synth1 = [st|
 `include "#{ddir}/data/cells_cmos.v"
 `include "#{ddir}/data/cells_cyclone_v.v"
-- 
cgit