From d29813263852c866f20f88504860120820499411 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 3 Dec 2019 20:03:17 +0000 Subject: Do not run counter example if no rerunner is specified --- src/Verismith/Tool/Template.hs | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/Verismith/Tool/Template.hs') diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index 0b63e91..ffa7240 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -26,6 +26,7 @@ module Verismith.Tool.Template where import Control.Lens ((^..)) +import Data.Maybe (fromMaybe) import Data.Text (Text) import qualified Data.Text as T import Prelude hiding (FilePath) @@ -136,11 +137,11 @@ synth_design -part xc7k70t -top #{top} write_verilog -force #{outf} |] -sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> b -> SourceInfo -> Text -sbyConfig datadir sim1 sim2 (SourceInfo top _) = [st|[options] +sbyConfig :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> SourceInfo -> Text +sbyConfig mt datadir sim1 sim2 (SourceInfo top _) = [st|[options] multiclock on mode prove -aigsmt none +aigsmt #{fromMaybe "none" mt} [engines] abc pdr -- cgit