From d821bbe66596b402a93c3189d5497e4d287f6a83 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 14 Nov 2019 19:48:38 +0000
Subject: Support proper Quartus Pro version

---
 src/Verismith/Tool/Template.hs | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

(limited to 'src/Verismith/Tool/Template.hs')

diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs
index 5402702..3bd5a2d 100644
--- a/src/Verismith/Tool/Template.hs
+++ b/src/Verismith/Tool/Template.hs
@@ -16,6 +16,7 @@ module Verismith.Tool.Template
     ( yosysSynthConfigStd
     , yosysSatConfig
     , yosysSimConfig
+    , quartusLightSynthConfig
     , quartusSynthConfig
     , xstSynthConfig
     , vivadoSynthConfig
@@ -77,10 +78,10 @@ yosysSimConfig = [st|read_verilog rtl.v; proc;;
 rename mod mod_rtl
 |]
 
-quartusSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text
-quartusSynthConfig q sdc top fp = [st|load_package flow
+quartusLightSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text
+quartusLightSynthConfig q sdc top fp = [st|load_package flow
 
-project_new #{top}
+project_new -overwrite #{top}
 
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name SYSTEMVERILOG_FILE #{toTextIgnore fp}
@@ -98,6 +99,25 @@ execute_module -tool eda -args "--simulation --tool=vcs"
 project_close
 |]
 
+quartusSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text
+quartusSynthConfig q sdc top fp = [st|load_package flow
+
+project_new -overwrite #{top}
+
+set_global_assignment -name FAMILY "Cyclone 10 GX"
+set_global_assignment -name SYSTEMVERILOG_FILE #{toTextIgnore fp}
+set_global_assignment -name TOP_LEVEL_ENTITY #{top}
+set_global_assignment -name SDC_FILE #{toTextIgnore sdc}
+set_global_assignment -name INI_VARS "qatm_force_vqm=on;"
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
+set_instance_assignment -name VIRTUAL_PIN ON -to *
+
+execute_module -tool syn
+execute_module -tool eda -args "--simulation --tool=vcs"
+
+project_close
+|]
+
 xstSynthConfig :: Text -> Text
 xstSynthConfig top = [st|run
 -ifn #{top}.prj -ofn #{top} -p artix7 -top #{top}
-- 
cgit