From 39dfa92affb1271dc6f714dfca0e13ba72e72e24 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 7 Apr 2020 01:31:45 +0100 Subject: Add annotations and make it compile again --- src/Verismith/Tool/Identity.hs | 4 ++-- src/Verismith/Tool/Quartus.hs | 4 ++-- src/Verismith/Tool/QuartusLight.hs | 4 ++-- src/Verismith/Tool/Vivado.hs | 4 ++-- src/Verismith/Tool/XST.hs | 4 ++-- src/Verismith/Tool/Yosys.hs | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) (limited to 'src/Verismith/Tool') diff --git a/src/Verismith/Tool/Identity.hs b/src/Verismith/Tool/Identity.hs index 9e436f3..8f6901f 100644 --- a/src/Verismith/Tool/Identity.hs +++ b/src/Verismith/Tool/Identity.hs @@ -25,8 +25,8 @@ import Verismith.Tool.Internal import Verismith.Verilog.AST import Verismith.Verilog.CodeGen -data Identity = Identity { identityDesc :: {-# UNPACK #-} !Text - , identityOutput :: {-# UNPACK #-} !FilePath +data Identity = Identity { identityDesc :: !Text + , identityOutput :: !FilePath } deriving (Eq) diff --git a/src/Verismith/Tool/Quartus.hs b/src/Verismith/Tool/Quartus.hs index fd999ee..e6624eb 100644 --- a/src/Verismith/Tool/Quartus.hs +++ b/src/Verismith/Tool/Quartus.hs @@ -27,8 +27,8 @@ import Verismith.Verilog.AST import Verismith.Verilog.CodeGen data Quartus = Quartus { quartusBin :: !(Maybe FilePath) - , quartusDesc :: {-# UNPACK #-} !Text - , quartusOutput :: {-# UNPACK #-} !FilePath + , quartusDesc :: !Text + , quartusOutput :: !FilePath } deriving (Eq) diff --git a/src/Verismith/Tool/QuartusLight.hs b/src/Verismith/Tool/QuartusLight.hs index 881ef8e..f703da0 100644 --- a/src/Verismith/Tool/QuartusLight.hs +++ b/src/Verismith/Tool/QuartusLight.hs @@ -27,8 +27,8 @@ import Verismith.Verilog.AST import Verismith.Verilog.CodeGen data QuartusLight = QuartusLight { quartusLightBin :: !(Maybe FilePath) - , quartusLightDesc :: {-# UNPACK #-} !Text - , quartusLightOutput :: {-# UNPACK #-} !FilePath + , quartusLightDesc :: !Text + , quartusLightOutput :: !FilePath } deriving (Eq) diff --git a/src/Verismith/Tool/Vivado.hs b/src/Verismith/Tool/Vivado.hs index e3d2538..35cda2e 100644 --- a/src/Verismith/Tool/Vivado.hs +++ b/src/Verismith/Tool/Vivado.hs @@ -27,8 +27,8 @@ import Verismith.Verilog.AST import Verismith.Verilog.CodeGen data Vivado = Vivado { vivadoBin :: !(Maybe FilePath) - , vivadoDesc :: {-# UNPACK #-} !Text - , vivadoOutput :: {-# UNPACK #-} !FilePath + , vivadoDesc :: !Text + , vivadoOutput :: !FilePath } deriving (Eq) diff --git a/src/Verismith/Tool/XST.hs b/src/Verismith/Tool/XST.hs index 4a4921c..2bec7d9 100644 --- a/src/Verismith/Tool/XST.hs +++ b/src/Verismith/Tool/XST.hs @@ -30,8 +30,8 @@ import Verismith.Verilog.AST import Verismith.Verilog.CodeGen data XST = XST { xstBin :: !(Maybe FilePath) - , xstDesc :: {-# UNPACK #-} !Text - , xstOutput :: {-# UNPACK #-} !FilePath + , xstDesc :: !Text + , xstOutput :: !FilePath } deriving (Eq) diff --git a/src/Verismith/Tool/Yosys.hs b/src/Verismith/Tool/Yosys.hs index 3632f37..9f536b7 100644 --- a/src/Verismith/Tool/Yosys.hs +++ b/src/Verismith/Tool/Yosys.hs @@ -39,8 +39,8 @@ import Verismith.Verilog.CodeGen import Verismith.Verilog.Mutate data Yosys = Yosys { yosysBin :: !(Maybe FilePath) - , yosysDesc :: {-# UNPACK #-} !Text - , yosysOutput :: {-# UNPACK #-} !FilePath + , yosysDesc :: !Text + , yosysOutput :: !FilePath } deriving (Eq) -- cgit