From feaf70849a93c60379104a6b4c1e7ee05afab340 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 19 May 2021 22:13:22 +0100
Subject: Add new simulation for EMI

---
 src/Verismith/Tool/Icarus.hs | 67 +++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 63 insertions(+), 4 deletions(-)

(limited to 'src/Verismith/Tool')

diff --git a/src/Verismith/Tool/Icarus.hs b/src/Verismith/Tool/Icarus.hs
index 8504640..da387dc 100644
--- a/src/Verismith/Tool/Icarus.hs
+++ b/src/Verismith/Tool/Icarus.hs
@@ -12,6 +12,7 @@ module Verismith.Tool.Icarus
   ( Icarus (..),
     defaultIcarus,
     runSimIc,
+    runSimIcEMI,
     runSimIcEC,
   )
 where
@@ -175,6 +176,45 @@ tbModule bss top =
   where
     inConcat = (RegConcat . filter (/= (Id "clk")) $ (Id . fromPort <$> (top ^. modInPorts)))
 
+tbModule' :: [Identifier] -> [ByteString] -> (ModDecl ann) -> (Verilog ann)
+tbModule' ids bss top =
+  Verilog
+    [ instantiateMod top $
+        ModDecl
+          "testbench"
+          []
+          []
+          [ Initial $
+              fold
+                [ BlockAssign (Assign "clk" Nothing 0),
+                  BlockAssign (Assign inConcat Nothing 0),
+                  BlockAssign (Assign inIds Nothing 0)
+                ]
+                <> fold
+                  ( ( \r ->
+                        TimeCtrl
+                          10
+                          (Just $ BlockAssign (Assign inConcat Nothing r))
+                    )
+                      . fromInteger
+                      . fromBytes <$> bss
+                  )
+                <> (TimeCtrl 10 . Just . SysTaskEnable $ Task "finish" []),
+            Always . TimeCtrl 5 . Just $
+              BlockAssign
+                (Assign "clk" Nothing (UnOp UnNot (Id "clk"))),
+            Always . EventCtrl (EPosEdge "clk") . Just . SysTaskEnable $
+              Task "strobe" ["%b", Id "y"]
+          ]
+          []
+    ]
+  where
+    inConcat = (RegConcat
+                . filter (flip notElem $ fmap Id ids)
+                . filter (/= (Id "clk"))
+                $ (Id . fromPort <$> (top ^. modInPorts)))
+    inIds = RegConcat $ fmap Id ids
+
 counterTestBench :: CounterEg -> (ModDecl ann) -> (Verilog ann)
 counterTestBench (CounterEg _ states) m = tbModule filtered m
   where
@@ -230,16 +270,35 @@ runSimIc ::
   -- | Synthesis tool to be tested.
   b ->
   -- | Original generated program to test.
-  (SourceInfo ann) ->
+  SourceInfo ann ->
   -- | Test vectors to be passed as inputs to the generated Verilog.
   [ByteString] ->
-  -- | What the correct output should be. If
-  -- 'Nothing' is passed, then just return 'Pass
-  -- ByteString' with the answer.
+  -- | What the correct output should be. If 'Nothing' is passed, then just return 'Pass ByteString'
+  -- with the answer.
   Maybe ByteString ->
   ResultSh ByteString
 runSimIc = runSimIc' tbModule
 
+runSimIcEMI ::
+  (Synthesiser b, Show ann) =>
+  -- | EMI Ids
+  [Identifier] ->
+  -- | Data directory.
+  FilePath ->
+  -- | Icarus simulator.
+  Icarus ->
+  -- | Synthesis tool to be tested.
+  b ->
+  -- | Original generated program to test.
+  SourceInfo ann ->
+  -- | Test vectors to be passed as inputs to the generated Verilog.
+  [ByteString] ->
+  -- | What the correct output should be. If 'Nothing' is passed, then just return 'Pass ByteString'
+  -- with the answer.
+  Maybe ByteString ->
+  ResultSh ByteString
+runSimIcEMI ids = runSimIc' (tbModule' ids)
+
 runSimIcEC ::
   (Synthesiser b, Show ann) =>
   FilePath ->
-- 
cgit