From 326048aeac6f846d8ad52c2a66f73219426f8bea Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Mon, 26 Apr 2021 11:38:55 +0100
Subject: Fix parser for a larger set of inputs

- Added support for parameter parsing
- Added support for parameter declaration for instantiations
- Fix parsing of @(*)
- Fix parsing of `timescale
- Add parsing for case statements with default
---
 src/Verismith/Verilog/Internal.hs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/Verismith/Verilog/Internal.hs')

diff --git a/src/Verismith/Verilog/Internal.hs b/src/Verismith/Verilog/Internal.hs
index d06fc5f..ce4cbce 100644
--- a/src/Verismith/Verilog/Internal.hs
+++ b/src/Verismith/Verilog/Internal.hs
@@ -62,6 +62,7 @@ testBench =
       wireDecl "c",
       ModInst
         "and"
+        []
         "and_gate"
         [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"],
       Initial $
-- 
cgit