From 472aedf5daeb1cb0d095a63eacf259b798f56586 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Mon, 16 Mar 2020 13:12:30 +0000
Subject: WIP changes to the AST types

---
 src/Verismith/Verilog/Internal.hs | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'src/Verismith/Verilog/Internal.hs')

diff --git a/src/Verismith/Verilog/Internal.hs b/src/Verismith/Verilog/Internal.hs
index 0644d95..0ebc626 100644
--- a/src/Verismith/Verilog/Internal.hs
+++ b/src/Verismith/Verilog/Internal.hs
@@ -32,28 +32,28 @@ import           Control.Lens
 import           Data.Text             (Text)
 import           Verismith.Verilog.AST
 
-regDecl :: Identifier -> ModItem
+regDecl :: Identifier -> (ModItem ann)
 regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing
 
-wireDecl :: Identifier -> ModItem
+wireDecl :: Identifier -> (ModItem ann)
 wireDecl i = Decl Nothing (Port Wire False (Range 1 0) i) Nothing
 
 -- | Create an empty module.
-emptyMod :: ModDecl
+emptyMod :: (ModDecl ann)
 emptyMod = ModDecl "" [] [] [] []
 
 -- | Set a module name for a module declaration.
-setModName :: Text -> ModDecl -> ModDecl
+setModName :: Text -> (ModDecl ann) -> (ModDecl ann)
 setModName str = modId .~ Identifier str
 
 -- | Add a input port to the module declaration.
-addModPort :: Port -> ModDecl -> ModDecl
+addModPort :: Port -> (ModDecl ann) -> (ModDecl ann)
 addModPort port = modInPorts %~ (:) port
 
-addModDecl :: ModDecl -> Verilog -> Verilog
+addModDecl :: (ModDecl ann) -> (Verilog ann) -> (Verilog ann)
 addModDecl desc = _Wrapped %~ (:) desc
 
-testBench :: ModDecl
+testBench :: (ModDecl ann)
 testBench = ModDecl
     "main"
     []
@@ -71,7 +71,7 @@ testBench = ModDecl
     ]
     []
 
-addTestBench :: Verilog -> Verilog
+addTestBench :: (Verilog ann) -> (Verilog ann)
 addTestBench = addModDecl testBench
 
 defaultPort :: Identifier -> Port
@@ -80,7 +80,7 @@ defaultPort = Port Wire False (Range 1 0)
 portToExpr :: Port -> Expr
 portToExpr (Port _ _ _ i) = Id i
 
-modName :: ModDecl -> Text
+modName :: (ModDecl ann) -> Text
 modName = getIdentifier . view modId
 
 yPort :: Identifier -> Port
-- 
cgit